https://github.com/jack74387/single-cycle-8-bit-cpu
Single-Cycle 8-bit CPU designed for basic instruction execution with Logisim.
https://github.com/jack74387/single-cycle-8-bit-cpu
circuit-design computer-organization-and-design cpu single-cycle
Last synced: 3 months ago
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Single-Cycle 8-bit CPU designed for basic instruction execution with Logisim.
- Host: GitHub
- URL: https://github.com/jack74387/single-cycle-8-bit-cpu
- Owner: jack74387
- Created: 2025-02-09T15:13:24.000Z (over 1 year ago)
- Default Branch: main
- Last Pushed: 2025-02-09T16:27:10.000Z (over 1 year ago)
- Last Synced: 2025-04-05T06:29:22.578Z (about 1 year ago)
- Topics: circuit-design, computer-organization-and-design, cpu, single-cycle
- Homepage:
- Size: 115 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# Single-Cycle-8-bit-CPU
This repository contains the design and implementation of a single-cycle 8-bit processor with only two registers, developed as part of the course project.
## Instruction Set Architecture (ISA)
The processor follows a simple instruction encoding scheme where the operation can be identified by examining the top bits of each byte.
### Key Features
- **Separate instruction and data memory**
- **Two general-purpose registers (`$ra`, `$rb`)**
- Supports arithmetic, logical, and branching instructions.
### Instruction Encoding Table
Bit
7
6
5
4
3
2
1
0
Description
nop
00000000
No operation
and
00100rdrarb
$rd = $ra & $rb
or
00101rdrarb
$rd = $ra | $rb
add
00110rdrarb
$rd = $ra + $rb
sub
00111rdrarb
$rd = $ra - $rb
lw
010rdimmediate
$rd = MEM[imm]
ori
101rdimmediate
$rd = $rd | imm
beq
111offset
Branch if $ra == $rb
---
#### Notes
- **nop:** No operation is performed.
- **Arithmetic operations:** Support basic logical and arithmetic functions (`and`, `or`, `add`, `sub`).
- **lw:** Loads data from memory into the register `$rd`.(**immediate uses un-signed extension**)
- **ori:** Bitwise OR between the register and immediate value.(**immediate uses un-signed extension**)
- **beq:** Branches to an offset if the two registers are equal.(**offset uses signed extension**)
### Branching Behavior
The `beq` instruction operates similarly to MIPS:
```asm
if $ra == $rb:
PC = PC + 1 + offset
else:
PC = PC + 1
```
---
### CPU Circuit Diagram
---
### How to Build and Simulate
- **Use Logisim to simulate this project:**
1. Clone the repository:
```bash
git clone https://github.com/jack74387/Single-Cycle-8-bit-CPU.git
```
2. Open the circuit in **Logisim**:
- download and install [Logisim](https://github.com/logisim-evolution/logisim-evolution?tab=readme-ov-file)
- Open `single-cycle-cpu.circ` from the project directory.
3. Run the simulation:
- Click the **Clock** icon to step through instructions manually.
- Observe the changes in registers and memory for each cycle.