https://github.com/jasonbrave/microsoc

RISC-V SoC
https://github.com/jasonbrave/microsoc

microcontroller risc-v riscv soc system-on-chip systemverilog uart verilog

Last synced: 17 days ago
JSON representation

RISC-V SoC

• Host: GitHub
• URL: https://github.com/jasonbrave/microsoc
• Owner: JasonBrave
• Created: 2023-04-24T00:29:19.000Z (about 2 years ago)
• Default Branch: main
• Last Pushed: 2023-09-04T21:37:59.000Z (over 1 year ago)
• Last Synced: 2025-02-13T10:24:19.105Z (2 months ago)
• Topics: microcontroller, risc-v, riscv, soc, system-on-chip, systemverilog, uart, verilog
• Language: SystemVerilog
• Homepage:
• Size: 37.1 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:

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