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https://github.com/jasonlin316/RISC-V-CPU

A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
https://github.com/jasonlin316/RISC-V-CPU

chip gate-level place-and-route processor risc-v riscv32 tape-out vector verilog

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A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.

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