https://github.com/jasonlin316/RISC-V-CPU

A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
https://github.com/jasonlin316/RISC-V-CPU

chip gate-level place-and-route processor risc-v riscv32 tape-out vector verilog

Last synced: 3 months ago
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A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.

• Host: GitHub
• URL: https://github.com/jasonlin316/RISC-V-CPU
• Owner: jasonlin316
• Created: 2019-05-12T07:14:07.000Z (over 5 years ago)
• Default Branch: master
• Last Pushed: 2019-12-02T17:08:52.000Z (almost 5 years ago)
• Last Synced: 2024-06-29T07:58:13.273Z (4 months ago)
• Topics: chip, gate-level, place-and-route, processor, risc-v, riscv32, tape-out, vector, verilog
• Language: Verilog
• Homepage:
• Size: 20.2 MB
• Stars: 97
• Watchers: 6
• Forks: 22
• Open Issues: 2

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