https://github.com/jbilander/denise_to_fpga
A small adapter-board that connects 12-bit RGB, 14 MHz CLK, PIXELSW and SYNC-signals on Denise to a FPGA-board via a 5V-tolerant buffer.
https://github.com/jbilander/denise_to_fpga
Last synced: 4 months ago
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A small adapter-board that connects 12-bit RGB, 14 MHz CLK, PIXELSW and SYNC-signals on Denise to a FPGA-board via a 5V-tolerant buffer.
- Host: GitHub
- URL: https://github.com/jbilander/denise_to_fpga
- Owner: jbilander
- License: cc-by-sa-4.0
- Created: 2023-08-19T18:59:03.000Z (almost 3 years ago)
- Default Branch: main
- Last Pushed: 2024-07-29T10:21:19.000Z (almost 2 years ago)
- Last Synced: 2025-02-06T16:04:55.920Z (over 1 year ago)
- Homepage:
- Size: 2.79 MB
- Stars: 2
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# Denise_to_FPGA
A small adapter-board that connects 12-bit RGB, 14 MHz CLK, PIXELSW and SYNC-signals on Denise to a FPGA-board via a 5V-tolerant buffer.
A synchronous 14 MHz clock is generated from `C7M XOR CDAC` by using a `74LVC1G86`-chip. This will be fed into the FPGA's PLL.
Board is two layers.
WORK IN PROGRESS, NOT FULLY TESTED YET!
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BOM Rev. A
---------
Designator | Name/Value | Package | Notes
-|-|-|-|
U1 | Voltage Regulator 3.3V,
LM1117-3.3 or
AMS1117-3.3 | SOT-223 | 3.3V 1A Low Drop-Out (LDO) [Voltage regulator](https://www.aliexpress.com/item/32869037691.html).
U2,U3 | Bus Transceiver 74LVC245A | TSSOP-20 | [74LVC245APW-T](https://www.mouser.com/ProductDetail/771-74LVC245APW-T)
U4 | XOR Gate 74LVC1G86 | SOT-353 | [74LVC1G86](https://www.mouser.com/ProductDetail/621-74LVC1G86QSE-7)
U5 | 48 pcs TH socket pins | 100 Pcs | IC Leads Receptacle, Length 9.7 mm gold or nickel plated.
[100 pcs](https://www.aliexpress.com/item/1005002830101899.html)
[300 pcs](https://www.aliexpress.com/item/1005004707554342.html)
[1000 pcs](https://www.aliexpress.com/item/32972142300.html)
[1000 pcs](https://www.aliexpress.com/item/32791545218.html)
C1,C2 | Capacitor 10uF | 1206 | Caps for Voltage Regulator
C3-C6 | Capacitor 0.1uF = 100nF | 0805 | Decoupling caps
R1 | 22 or 33 Ω Resistor | 0805 | 22 or 33 Ω series resistor to [avoid reflections](https://embeddeddesignblog.blogspot.com/2022/07/why-do-we-need-series-resistor-on-clock.html) on the 14 MHz CLK
J1 | CDAC/CSYNC Two-Pin Header 2.54mm pitch | 2.54mm pitch | Connect a fly-lead here for old Rev. 3 A500 Motherboard that doesn't have these signals at the Denise socket.
J2 | VSYNC/HSYNC Two-Pin Header 2.54mm pitch | 2.54mm pitch | Connect a fly-lead here with connection to the Horizontal and Vertical sync on DB23-backside.
J3 | FPC connector, Right Angle, bottom contact | 0.5mm pitch, 40 positions | [TE Connectivity 4-1734592-0](https://www.mouser.com/ProductDetail/571-4-1734592-0) or [40p here](https://www.aliexpress.com/item/10000000478377.html)
***
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