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https://github.com/jbush001/LispMicrocontroller
A microcontroller that natively executes a simple LISP dialect
https://github.com/jbush001/LispMicrocontroller
cpu fpga hardware lisp microcontroller verilog
Last synced: about 2 months ago
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A microcontroller that natively executes a simple LISP dialect
- Host: GitHub
- URL: https://github.com/jbush001/LispMicrocontroller
- Owner: jbush001
- License: apache-2.0
- Created: 2011-12-28T19:39:57.000Z (about 13 years ago)
- Default Branch: master
- Last Pushed: 2024-01-22T01:50:41.000Z (12 months ago)
- Last Synced: 2024-11-07T22:02:29.957Z (about 2 months ago)
- Topics: cpu, fpga, hardware, lisp, microcontroller, verilog
- Language: Python
- Homepage:
- Size: 366 KB
- Stars: 89
- Watchers: 9
- Forks: 12
- Open Issues: 7
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Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
[![CI](https://github.com/jbush001/LispMicrocontroller/workflows/CI/badge.svg)](https://github.com/jbush001/LispMicrocontroller/actions?query=workflow%3ACI)
[![Codacy Badge](https://api.codacy.com/project/badge/Grade/8f4aff19a2d242f892acc10b98950f46)](https://www.codacy.com/app/jbush001/LispMicrocontroller?utm_source=github.com&utm_medium=referral&utm_content=jbush001/LispMicrocontroller&utm_campaign=Badge_Grade)This is a simple microcontroller that runs a compiled LISP dialect. Details of operation are in the [wiki](https://github.com/jbush001/LispMicrocontroller/wiki).
## Running in simulation
This uses Icarus Verilog for simulation (http://iverilog.icarus.com/). Tests are located in the tests/ directory. Run them as follows:
make test
The test runner searches files for patterns that begin with 'CHECK:'. The output of the program will be compared to whatever comes after this declaration. If they do not match, an error will be flagged.
### Manually running a program
* Compile the LISP sources.
This produces two files: program.hex, which has the raw program machine code and is loaded by the simulator, and program.lst, which is informational and shows details of the generated code. For example:./compile.py tests/test1.lisp
Note that any writes to register index 0 will be printed to standard out by the simulation test harness, which is how most simulation tests work.
* Run simulation.
The simulator will read rom.hex each time it starts.vvp sim.vvp
## Running in hardware
This has only been tested under Quartus/Altera with the Cyclone II starter kit. There are a couple of projects located
under the fpga/ directory:
- 7seg: simple program that displays numbers on the 4-digit, 7 segment display
- game: a little arcade-style demo with animated sprites### To build:
* Compile the LISP sources.
These are located in the project directory, but must be compiled from the top directory.
For example, from LispMicrocontroller/./compile.py fpga/game/game.lisp
rom.hex will be created in the top level LispMicrocontroller/ directory.
* Synthesize the design
Open the program file (for example, fpga/game/game.qpf). Note that the synthesis tools will
read rom.hex to create the values for program ROM. If you recompile the LISP sources (thereby changing rom.hex), the design must be re-synthesized.* Run using the programmer included with Quartus.