https://github.com/jc-ll/reggae_v2
https://github.com/jc-ll/reggae_v2
Last synced: 1 day ago
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- Host: GitHub
- URL: https://github.com/jc-ll/reggae_v2
- Owner: JC-LL
- Created: 2022-01-27T14:54:25.000Z (over 3 years ago)
- Default Branch: main
- Last Pushed: 2022-02-01T11:07:59.000Z (over 3 years ago)
- Last Synced: 2025-02-07T22:49:56.313Z (4 months ago)
- Language: Ruby
- Size: 11.3 MB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# Reggae : FPGA register map VHDL generation
## What is it ?
Reggae is a simple tool that generates a System-on-Chip architecture from a a description of its memory map.
The tool is especially targeted to quick prototyping of early demonstrators on FPGA.
## Memory map specification : s-expression based
The memory map, specified by the user, is described in a s-expression based file.
A full example is provided in tests directory. A simple IP interface can be as simple as :
```
(ip "switches"
(range 0x1 0x1)
(reg "switches"
(address 0x1)
(sampling "sig_switches")
(init 0xcafebabe)
)
)
```
Here we have simply asked Reggae to generate an IP named "switches", with a single register, also named "switches", that reset to default value 0xcafebabe. This register samples a signal named "sig_switches", that will be user-defined, probably connected to actual switches !
More detailed low-level specification can be used : bits and bitfields, toggling etc
```
(ip "robot"
(range 0x202 0x203)
(reg "control"
(address 0x202)
(size 5)
(init 0xdeadbeef)
(bit 0
(name "go")
(toggling true)
)
(bit 1
(name "stop")
)
(bit 2
(name "light_on")
)
(bit 3
(name "turn_right")
)
(bit 4
(name "turn_left")
)
)
(reg "status"
(address 0x203)
(init 0x0)
(bit 0
(name "stopped")
(sampling "robot_stopped")
)
(bit 1
(name "failure")
(sampling "robot_failure")
)
(bitfield 2..31
(name "loch")
(sampling "robot_loch")
)
)
)
```
Reggae will then create the following architecture, as well as testbench and synthesis files (for Vivado, today for Nexysa7).
## SoC architecture
The SoC template is given as example below.
