https://github.com/jdibenes/fpga_modules
Collection of FPGA modules for video capture and processing.
https://github.com/jdibenes/fpga_modules
fpga matlab tcl ultrascale-plus vhdl video-processing vivado zcu102
Last synced: 5 months ago
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Collection of FPGA modules for video capture and processing.
- Host: GitHub
- URL: https://github.com/jdibenes/fpga_modules
- Owner: jdibenes
- License: mit
- Created: 2020-07-08T18:59:46.000Z (about 6 years ago)
- Default Branch: master
- Last Pushed: 2023-02-03T23:46:01.000Z (over 3 years ago)
- Last Synced: 2025-06-15T08:06:52.753Z (about 1 year ago)
- Topics: fpga, matlab, tcl, ultrascale-plus, vhdl, video-processing, vivado, zcu102
- Language: Tcl
- Homepage:
- Size: 98.6 KB
- Stars: 4
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# FPGA Modules
This is a collection of FPGA designs for video capture and processing. All modules have been tested on a ZCU102 Evaluation Board with two IMX274 (LI-IMX274MIPI-FMC) cameras. All tcl scripts contain block diagrams for Vivado 2017.4. To build the block diagrams, create a new project in Vivado (File->New Project...) then, after the project has been created, select Tools->Run Tcl Script and select the tcl script. For an example of a module integrating AXI-Stream, AXI, and AXI-Lite interfaces see l2dma.