https://github.com/jiahaoxiang2000/bitsliced_optimize

Optimal Low-Latency Implementation of Bitsliced Cipher for RISC Processors
https://github.com/jiahaoxiang2000/bitsliced_optimize

cipher embedded-systems implementation

Last synced: about 2 months ago
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Optimal Low-Latency Implementation of Bitsliced Cipher for RISC Processors

• Host: GitHub
• URL: https://github.com/jiahaoxiang2000/bitsliced_optimize
• Owner: jiahaoxiang2000
• License: apache-2.0
• Created: 2024-05-10T08:08:07.000Z (8 months ago)
• Default Branch: main
• Last Pushed: 2024-11-17T09:27:50.000Z (about 2 months ago)
• Last Synced: 2024-11-17T10:27:47.347Z (about 2 months ago)
• Topics: cipher, embedded-systems, implementation
• Language: Jupyter Notebook
• Homepage:
• Size: 35.2 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: readme.md
  • License: LICENSE

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README

        
# Optimal Low-Latency Implementation of Bitsliced SPN-Cipher on 32-bit Processors

This repository contains the implementation and evaluation framework for optimizing bitsliced SPN-cipher implementations on 32-bit processors like ARM Cortex-M4. The work focuses on both theoretical optimization techniques and practical performance evaluation.

## Contents

The project consists of three main components:

- `non-linear-layer`: Implementation of a novel S-box optimization technique using the Bit-slice Gate Complexity (BGC) model that improves the efficiency of the non-linear substitution layer.

- `linear-layer`: Implementation of the Optimization of Permutation Operations (OPO) algorithm for optimizing the linear permutation layer. The key implementation is in [optimize_permutation.ipynb](linear-layer/optimize_permutation.ipynb).

- `LCB`: A comprehensive benchmarking framework for evaluating lightweight block cipher implementations on microcontrollers. Contains the experimental data and performance measurements discussed in the paper.

## Getting Started

- See `non-linear-layer/readme.md` for S-box optimization

- See `linear-layer/readme.md` for permutation optimization

- See `LCB/README.md` for performance evaluation framework

## Tested Platforms

The optimizations target 32-bit microcontroller platforms:

- ARM Cortex-M4 based boards (STM32L475)

- ESP32-S3 based boards