https://github.com/jiegec/fpnew-wrapper

A chisel3 wrapper for pulp-platform/fpnew
https://github.com/jiegec/fpnew-wrapper

chisel3 fpu hardware-libraries

Last synced: 8 days ago
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A chisel3 wrapper for pulp-platform/fpnew

• Host: GitHub
• URL: https://github.com/jiegec/fpnew-wrapper
• Owner: jiegec
• License: mit
• Created: 2020-04-06T11:23:48.000Z (over 4 years ago)
• Default Branch: master
• Last Pushed: 2020-04-10T15:26:58.000Z (over 4 years ago)
• Last Synced: 2024-10-26T22:48:36.466Z (about 2 months ago)
• Topics: chisel3, fpu, hardware-libraries
• Language: SystemVerilog
• Homepage:
• Size: 83 KB
• Stars: 8
• Watchers: 3
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# FPnew Wrapper

A chisel3 wrapper for [pulp-platform/fpnew](https://github.com/pulp-platform/fpnew). Use the same method how ucb-bar/ariane-wrapper wraps Ariane.

This project uses verilator to preprocess fpnew sources to get rid of compiler derivatives to create a self contained verilog file.

## Installation

You can either:

1. Add this project to subdirectory and update your `build.sbt`.

2. Run `sbt publishLocal` and use `"jia.je" %% "fpnew" % "1.0-SNAPSHOT"` in libraryDependencies.

## Caveats

1. When pipelineStages is configured other than zero and verilator is used for simulation, `-Wno-BLKANDNBLK` must be passed to verilator. See `src/test/scala/fpnew/FPNewTest.scala` for usage with chisel-iotesters.

## License

See `LICENSE`. This project wraps code from [pulp-platform/fpnew](https://github.com/pulp-platform/fpnew) which is licensed under SolderPad Hardware License.