https://github.com/jn513/fpga_basics
Basic FPGA demo circuits made in Verilog HDL, VHDL and SystemVerilog
https://github.com/jn513/fpga_basics
basic fpga learning verilog verilog-hdl vhdl vhdl-code
Last synced: about 2 months ago
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Basic FPGA demo circuits made in Verilog HDL, VHDL and SystemVerilog
- Host: GitHub
- URL: https://github.com/jn513/fpga_basics
- Owner: JN513
- License: mit
- Created: 2025-02-12T00:07:07.000Z (2 months ago)
- Default Branch: main
- Last Pushed: 2025-02-17T20:25:01.000Z (2 months ago)
- Last Synced: 2025-02-17T20:25:14.498Z (2 months ago)
- Topics: basic, fpga, learning, verilog, verilog-hdl, vhdl, vhdl-code
- Language: Verilog
- Homepage:
- Size: 41 KB
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- Contributing: CONTRIBUTING.md
- License: LICENSE
- Code of conduct: CODE_OF_CONDUCT.md
- Security: SECURITY.md
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README
# Verilog Basics
Basic FPGA demo circuits made in Verilog HDL, VHDL and SystemVerilog
# Roadmap
0 - blink
1 - led counter
2 - led shiffter
3 - button
4 - hamming code
5 - button modes
6 - semaphore
7 - 7 segment
8 - 7 segment semaphore
9 - simple clock
10 - sum
11 - calculator
## Project Official Language
The official language adopted by the project is Brazilian Portuguese; therefore, most of the documentation and commits are in this language.
## Contribution
If you'd like to contribute to the project, please feel free to do so. The [CONTRIBUTING.md](https://github.com/JN513/verilog_basics/blob/main/CONTRIBUTING.md) file contains the necessary instructions.
## License
This project is licensed under the [MIT license](https://github.com/JN513verilog-buses-implementations/blob/main/LICENSE), which grants full freedom for use.