https://github.com/jn513/verilog-buses-implementations

Popular bus implementations in Verilog HDL
https://github.com/jn513/verilog-buses-implementations

ahb apb avalon axi4 axi4-lite axi4-stream fpga i2c i2c-bus spi verilog verilog-hdl

Last synced: 5 months ago
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Popular bus implementations in Verilog HDL

• Host: GitHub
• URL: https://github.com/jn513/verilog-buses-implementations
• Owner: JN513
• License: mit
• Created: 2025-02-06T13:40:43.000Z (9 months ago)
• Default Branch: main
• Last Pushed: 2025-02-06T20:14:07.000Z (9 months ago)
• Last Synced: 2025-02-26T15:19:32.019Z (8 months ago)
• Topics: ahb, apb, avalon, axi4, axi4-lite, axi4-stream, fpga, i2c, i2c-bus, spi, verilog, verilog-hdl
• Language: Verilog
• Homepage:
• Size: 9.77 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • Contributing: CONTRIBUTING.md
  • Funding: .github/FUNDING.yml
  • License: LICENSE
  • Code of conduct: CODE_OF_CONDUCT.md
  • Security: SECURITY.md

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README

          
# Verilog Buses Implementations

Popular bus implementations in Verilog HDL.

## Project Official Language

The official language adopted by the project is Brazilian Portuguese; therefore, most of the documentation and commits are in this language.

## Contribution

If you'd like to contribute to the project, please feel free to do so. The [CONTRIBUTING.md](https://github.com/JN513/verilog-buses-implementations/blob/main/CONTRIBUTING.md) file contains the necessary instructions.

## License

This project is licensed under the [CERN-OHL-P-2.0 license](https://github.com/JN513verilog-buses-implementations/blob/main/LICENSE), which grants full freedom for use.