https://github.com/jofrfu/haw-v
Fork of a RISC-V compliant CPU, which originated in a project at the HAW Hamburg
https://github.com/jofrfu/haw-v
assembly c fpga linux risc-processor risc-v vhdl vivado xilinx-fpga
Last synced: about 1 year ago
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Fork of a RISC-V compliant CPU, which originated in a project at the HAW Hamburg
- Host: GitHub
- URL: https://github.com/jofrfu/haw-v
- Owner: jofrfu
- Created: 2018-08-14T18:59:24.000Z (almost 8 years ago)
- Default Branch: master
- Last Pushed: 2019-03-06T23:08:40.000Z (over 7 years ago)
- Last Synced: 2025-04-09T10:33:48.277Z (about 1 year ago)
- Topics: assembly, c, fpga, linux, risc-processor, risc-v, vhdl, vivado, xilinx-fpga
- Language: VHDL
- Homepage:
- Size: 31.9 MB
- Stars: 5
- Watchers: 0
- Forks: 3
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# HAW-V
This is a fork of a project at the HAW Hamburg. It includes a RISC-V compliant processor written in VHDL.
It's compact size allows it to be used in a variety of use cases from low power to high speed requirements.
In the scope of this project, only the RV32I instruction set was implemented.
Documentation can be found in /doc with a quick start guide for the Zedboard with Xilinx Zynq SoC (/doc/design_documentation/Instruction_Usage.pdf).