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https://github.com/karanraj06/riscv-32i-simulator
RISCV-32I Simulator for executing machine code with single cycle and pipelined processor design
https://github.com/karanraj06/riscv-32i-simulator
fastapi flask react risc-v
Last synced: 5 days ago
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RISCV-32I Simulator for executing machine code with single cycle and pipelined processor design
- Host: GitHub
- URL: https://github.com/karanraj06/riscv-32i-simulator
- Owner: Karanraj06
- Created: 2023-03-01T16:00:50.000Z (almost 2 years ago)
- Default Branch: main
- Last Pushed: 2024-04-19T08:18:31.000Z (10 months ago)
- Last Synced: 2024-04-19T19:28:29.610Z (10 months ago)
- Topics: fastapi, flask, react, risc-v
- Language: Python
- Homepage: https://riscv-32i-simulator-v2.netlify.app
- Size: 1.01 MB
- Stars: 6
- Watchers: 1
- Forks: 3
- Open Issues: 1
-
Metadata Files:
- Readme: README.md
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README
# RISCV-32I-Simulator
Functional Simulator for a subset of RISC-V Instruction Set. RISC-V is an open-source Instruction Set Architecture (ISA) that has gained popularity in recent years due to its simplicity and extensibility. The simulator reads encoded instructions from a memory file (machine code), decodes, executes, and writes back the results to a register file.
## Overview
The project implements a functional simulator for a subset of RISC-V Instruction Set using a single-cycle processor design.
The simulator has two components:
- Command Line Interface (CLI)
The CLI component is explained [here](single_cycle/README.md) detail
- Graphical User Interface (GUI) built with Flask and Tailwind
The webapp is available at the following url: http://karanraj.pythonanywhere.com/
## File Structure
```
.
├── README.md
├── docs
│ └── reference.docx
├── single_cycle
│ ├── README.md
│ ├── decode.py
│ ├── execute.py
│ ├── input.mc
│ ├── instruction_fetch.py
│ ├── main.py
│ ├── memory_access.py
│ ├── output.txt
│ ├── registers.py
│ └── write_back.py
├── single_cycle_webapp
│ │── README.md
│ │── app.py
│ │── ...
│ └── write_back.py
└── test
├── array_sum.mc
├── array_sum.s
├── bubble_sort.mc
├── bubble_sort.s
├── fibonacci.mc
└── fibonacci.s
```
The `single_cycle` folder contains the source code for the CLI component of the simulator. The `single_cycle_webapp` folder contains the source code for the GUI component of the simulator. The `test` folder contains some sample programs to test the simulator's correctness.
## Supported Instructions
The simulator supports the following instructions:
```
R-Type: ADD, SUB, XOR, OR, AND, SLL, SRL, SRA
I-Type: ADDI, XORI, ORI, ANDI, SLLI, SRLI, SRAI, LB, LH, LW, JALR
S-Type: SB, SH, SW
B-Type: BEQ, BNE, BGE, BLT
U-Type: AUIPC, LUI
J-Type: JAL
```
Each instruction performs a specific operation such as arithmetic, logical, or control flow. For example, the ADDI instruction adds an immediate value to a register.
## Group Members
[@AtharvaMulay25](https://github.com/AtharvaMulay25)
[@Karanraj06](https://github.com/Karanraj06)
[@nishad-dhuri-05](https://github.com/nishad-dhuri-05)
[@SumitPatil0404](https://github.com/SumitPatil0404)
## Documentation
Please refer to the `reference.docx` file in the `docs` folder for more information on how to use the simulator