https://github.com/kenny2github/v2mc

Synthesize Verilog to Minecraft redstone
https://github.com/kenny2github/v2mc

hdl minecraft redstone verilog yosys

Last synced: about 2 months ago
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Synthesize Verilog to Minecraft redstone

• Host: GitHub
• URL: https://github.com/kenny2github/v2mc
• Owner: Kenny2github
• License: gpl-3.0
• Created: 2023-02-21T05:43:12.000Z (almost 2 years ago)
• Default Branch: main
• Last Pushed: 2024-11-09T14:07:53.000Z (3 months ago)
• Last Synced: 2024-11-09T15:19:11.528Z (3 months ago)
• Topics: hdl, minecraft, redstone, verilog, yosys
• Language: Python
• Homepage:
• Size: 194 KB
• Stars: 3
• Watchers: 3
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE.txt

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README

        
# Verilog to Minecraft Redstone

This project provides Minecraft redstone as a synthesis target for Verilog

## Goal

Fully synthesize all synthesizable Verilog. This includes both combinational and sequential logic - flip-flops and all that jazz.

This project is purely for technology mapping, placement, routing, or some combination thereof. Analysis & elaboration of Verilog is done by Yosys, and technology mapping is done with Yosys.

## Dependencies

The following must be in your `PATH`:

* Python 3

* Yosys 0.47 built with Python support (`make ENABLE_PYOSYS=1 && make install`)

We require pyosys (`python3 setup.py install` at root of Yosys repository, which you should already have from building it) in order to access the Yosys internal representation of RTL designs.

We require the dependencies in `requirements.txt` in order to manipulate NBT structures.

## I/O Format

For input, we take one or more Verilog HDL design files. For output, we produce a Minecraft structure file.

## Technology mapping

Currently we map the following [Yosys internal cells](https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/formats/cell_library.html#rtl-cells) to custom primitives:

* `$dff, $sdff, $sdffe` → `MC_DFF31`

* `$adff, $adffe` → `MC_ADFF31`

Redstone signal strength is the main factor leading to the limitation of `WIDTH` to 31 (15 signal strength, in two directions, separated by a hard-powered block) when any input/output is a number of bits independent of `WIDTH`. The technology mapping process reduces, for example, a 64-bit `$dff` to two 31-bit and one 2-bit `MC_DFF31`s.

All others we allow `techmap` to map to [Yosys internal gates](https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/formats/cell_library.html#gates), which we then map to custom primitives: