https://github.com/liuqdev/8-bits-RISC-CPU-Verilog

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
https://github.com/liuqdev/8-bits-RISC-CPU-Verilog

cpu fsm risc verilog

Last synced: 3 months ago
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Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。

• Host: GitHub
• URL: https://github.com/liuqdev/8-bits-RISC-CPU-Verilog
• Owner: liuqdev
• License: mit
• Created: 2019-01-20T02:20:17.000Z (over 6 years ago)
• Default Branch: master
• Last Pushed: 2019-01-20T02:49:20.000Z (over 6 years ago)
• Last Synced: 2024-11-28T02:35:39.020Z (11 months ago)
• Topics: cpu, fsm, risc, verilog
• Language: Verilog
• Size: 7.08 MB
• Stars: 135
• Watchers: 3
• Forks: 42
• Open Issues: 2
• Metadata Files:
  • Readme: readme.rst
  • License: LICENSE

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