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https://github.com/ljlin/MIPS48PipelineCPU
5 stage pipelined MIPS-32 processor
https://github.com/ljlin/MIPS48PipelineCPU
architecture cpu mips mips-architecture verilog
Last synced: 3 months ago
JSON representation
5 stage pipelined MIPS-32 processor
- Host: GitHub
- URL: https://github.com/ljlin/MIPS48PipelineCPU
- Owner: ljlin
- Created: 2015-07-07T11:06:33.000Z (over 9 years ago)
- Default Branch: master
- Last Pushed: 2020-04-20T08:20:59.000Z (over 4 years ago)
- Last Synced: 2024-06-29T07:58:05.485Z (4 months ago)
- Topics: architecture, cpu, mips, mips-architecture, verilog
- Language: Verilog
- Homepage:
- Size: 1.78 MB
- Stars: 52
- Watchers: 4
- Forks: 11
- Open Issues: 0
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Metadata Files:
- Readme: README.md
Awesome Lists containing this project
- StarryDivineSky - ljlin/MIPS48PipelineCPU