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https://github.com/lsx-s-software/tiny-riscv-cpu
An implementation of RV32I ISA, including a single-cycle version and a pipelined version.
https://github.com/lsx-s-software/tiny-riscv-cpu
cpu pipeline risc-v verilog
Last synced: about 2 months ago
JSON representation
An implementation of RV32I ISA, including a single-cycle version and a pipelined version.
- Host: GitHub
- URL: https://github.com/lsx-s-software/tiny-riscv-cpu
- Owner: LSX-s-Software
- License: gpl-3.0
- Created: 2022-02-25T04:23:56.000Z (almost 3 years ago)
- Default Branch: master
- Last Pushed: 2022-06-10T01:32:44.000Z (over 2 years ago)
- Last Synced: 2023-03-06T20:42:47.827Z (almost 2 years ago)
- Topics: cpu, pipeline, risc-v, verilog
- Language: Verilog
- Homepage:
- Size: 5.13 MB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0