https://github.com/m13253/sbmips

Naïve MIPS32-like CPU design with pipeline on a Xilinx FPGA
https://github.com/m13253/sbmips

fpga mips mips32 verilog

Last synced: about 8 hours ago
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Naïve MIPS32-like CPU design with pipeline on a Xilinx FPGA

• Host: GitHub
• URL: https://github.com/m13253/sbmips
• Owner: m13253
• License: gpl-3.0
• Created: 2017-05-22T06:26:24.000Z (over 7 years ago)
• Default Branch: master
• Last Pushed: 2017-05-24T09:12:49.000Z (over 7 years ago)
• Last Synced: 2024-12-05T13:42:24.417Z (about 2 months ago)
• Topics: fpga, mips, mips32, verilog
• Language: Verilog
• Homepage:
• Size: 36.1 KB
• Stars: 1
• Watchers: 3
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: Readme.md
  • License: LICENSE

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README

        
# sbmips

Naïve MIPS32-like CPU design on a Xilinx FPGA

## Features

- Five-stage pipeline

- Data forwarding

- One-instruction delay slot

- No branch prediction

- No privileged instructions

- No interruptions or exceptions

Academic reference purpose only, contains bugs, not suitable for production.

## Implemented instructions

### R-Type

- `sll` - Logical left shift

- `srl` - Logical right shift

- `sra` - Arithmetical right shift

- `sllv` - Logical left shift by value

- `srlv` - Logical right shift by value

- `srav` - Arithmetical right shift by value

- `jr` - Jump by register

- `jalr` - Jump and link by register

- `add` - Add

- `addu` - Add without overflow check

- `sub` - Subtract

- `subu` - Subtract without overflow check

- `and` - Bitwise and

- `or` - Bitwise or

- `xor` - Bitwise exclusive or

- `nor` - Bitwise not or

- `slt` - Set if less than

- `sltu` - Set if unsigned less than

### I-Type

- `beq` - Branch if equal

- `bne` - Branch if not equal

- `addi` - Add immediate value

- `addiu` - Add immediate value without overflow check

- `slti` - Set if less than immediate value

- `sltiu` - Set if less than unsigned immediate value

- `andi` - Bitwise and immediate value

- `ori` - Bitwise or immediate value

- `xori` - Bitwise exclusive or immediate value

- `lui` - Load immediate value as upper half-word

- `lw` - Load word from memory

- `sw` - Store word from memory

### J-Type

- `j` - Jump

- `jal` - Jump and link

### Available pseudo-instructions

- `la` - Load address

- `li` - Load immediate value

- `move` - Move register

- `negu` - Negation

- `nop` - No operation

- `not` - Bitwise not

- `b` - Branch

- `bal` - Branch and link

- `beqz` - Branch if equal to zero

- `bnez` - Branch if not equal to zero

## Model

Development board: Digilent Nexys 3

FPGA chip: Xilinx Spartan-6 `xc6slx16-3csg324`

## I/O

- `clk (btn)` and `rst` are controlled by two buttons, so you can single-step over the program.

- `gclk` is driven by 100 MHz quartz crystal resonator.

- `led_sel` is bond to 8 switches.

- `led` powers the 4-digit seven-segmented display, showing values of different registers according to `led_sel`.

## License

Released under GNU General Public License version 3 (GPLv3).

See [LICENSE](LICENSE) for more information.