https://github.com/maltanar/fpga-tidbits

Chisel components for FPGA projects
https://github.com/maltanar/fpga-tidbits

chisel fpga hardware-libraries

Last synced: 4 months ago
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Chisel components for FPGA projects

• Host: GitHub
• URL: https://github.com/maltanar/fpga-tidbits
• Owner: maltanar
• License: bsd-2-clause
• Created: 2015-06-25T08:57:08.000Z (over 10 years ago)
• Default Branch: master
• Last Pushed: 2023-09-19T07:38:02.000Z (over 2 years ago)
• Last Synced: 2025-03-15T04:09:53.248Z (11 months ago)
• Topics: chisel, fpga, hardware-libraries
• Language: Verilog
• Homepage:
• Size: 822 KB
• Stars: 121
• Watchers: 9
• Forks: 27
• Open Issues: 1
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

          
# fpga-tidbits

A collection of Chisel hardware generators for small but useful components for FPGA projects. 

There is some documentation available on the ([wiki](https://github.com/maltanar/fpga-tidbits/wiki)), but is rather incomplete. The best source of information is taking a look at the source code (most components are pretty small) or sending me an ([e-mail](mailto:maltanar@gmail.com)).

Contributors and pull requests are welcome!