https://github.com/marekpikula/quartus-sv-gotchas
Document describing different gotchas in Intel Quartus SystemVerilog code synthesis.
https://github.com/marekpikula/quartus-sv-gotchas
quartus rtl systemverilog
Last synced: 3 months ago
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Document describing different gotchas in Intel Quartus SystemVerilog code synthesis.
- Host: GitHub
- URL: https://github.com/marekpikula/quartus-sv-gotchas
- Owner: MarekPikula
- License: cc-by-4.0
- Created: 2019-09-18T09:42:34.000Z (over 5 years ago)
- Default Branch: master
- Last Pushed: 2019-10-21T09:53:17.000Z (over 5 years ago)
- Last Synced: 2025-01-28T13:52:15.887Z (5 months ago)
- Topics: quartus, rtl, systemverilog
- Size: 28.3 KB
- Stars: 1
- Watchers: 2
- Forks: 1
- Open Issues: 1
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Metadata Files:
- Readme: README.md
- License: LICENSE.md
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README
# Intel Quartus SystemVerilog gotchas
In this document I would like to express my discontent with Intel Quartus SystemVerilog support and ways to work around the gotchas I stumbled upon, while porting [PULPissimo](https://github.com/pulp-platform/pulpissimo/) SoC system to Quartus.
The document is currently work in progress since the porting isn't finished yet, but the author wanted to make a catalog of all the little things he stumbled upon for future reference, while working on the code.
You can find it in [Intel Quartus SystemVerilog gotchas](Intel Quartus SystemVerilog gotchas.md) document.
All documents in this repository are licensed under Creative Commons Attribution 4.0 International ([CC-BY 4.0](https://creativecommons.org/licenses/by/4.0/deed)). A copy of the license is in [LICENSE](LICENSE.md) file.
You can find GitHub pages version [here](https://marekpikula.github.io/quartus-sv-gotchas/).