https://github.com/martinkindall/mips_cpu
Single Cycle 32 bit MIPS
https://github.com/martinkindall/mips_cpu
basys3 basys3-fpga fpga mips mips-cpu single-cycle single-cycle-processor systemverilog
Last synced: 2 months ago
JSON representation
Single Cycle 32 bit MIPS
- Host: GitHub
- URL: https://github.com/martinkindall/mips_cpu
- Owner: martinKindall
- Created: 2022-12-02T23:27:26.000Z (over 2 years ago)
- Default Branch: main
- Last Pushed: 2022-12-24T16:39:00.000Z (over 2 years ago)
- Last Synced: 2023-03-04T19:40:25.382Z (about 2 years ago)
- Topics: basys3, basys3-fpga, fpga, mips, mips-cpu, single-cycle, single-cycle-processor, systemverilog
- Language: SystemVerilog
- Homepage:
- Size: 280 KB
- Stars: 7
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
# MIPS 32 bits Single Cycle CPU
This project is based on the book [Digital Design and Computer Architecture](https://www.amazon.com/Digital-Design-Computer-Architecture-Harris/dp/0123944244/ref=sr_1_1?keywords=digital+design+and+computer+architecture&qid=1670106216&sprefix=digital+design%2Caps%2C178&sr=8-1) and its example for a MIPS cpu written in Systemverilog.
The designs are in the folder __sources_1__ and the top module is _MipsTopIO.sv_.
The program files are _twoPlusTwo.asm_ and _twoPlusTwo.dat_.
Video:
https://youtu.be/mYzHAQF_kyk