https://github.com/matth2k/nl-compiler
Frontend compiler for safety-net
https://github.com/matth2k/nl-compiler
aiger compilers eda verilog
Last synced: 3 months ago
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Frontend compiler for safety-net
- Host: GitHub
- URL: https://github.com/matth2k/nl-compiler
- Owner: matth2k
- License: apache-2.0
- Created: 2025-08-27T18:25:33.000Z (10 months ago)
- Default Branch: main
- Last Pushed: 2026-02-12T20:57:53.000Z (4 months ago)
- Last Synced: 2026-02-13T04:32:01.717Z (4 months ago)
- Topics: aiger, compilers, eda, verilog
- Language: Rust
- Homepage: https://matth2k.github.io/nl-compiler/
- Size: 59.6 KB
- Stars: 0
- Watchers: 0
- Forks: 1
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE-APACHE
Awesome Lists containing this project
README
[](https://matth2k.github.io/nl-compiler/)
[](https://crates.io/crates/nl-compiler)
# `nl-compiler`: Frontend Compiler for [Safety-Net](https://github.com/matth2k/safety-net)
## Getting Started
Below is a minimal example to get you started:
```verilog
module and_test (
a,
b,
y
);
input a;
wire a;
input b;
wire b;
output y;
wire y;
AND _0_ (
.A(a),
.B(b),
.Y(y)
);
endmodule
```
Save the above file to `and.v`.
`cargo run --example roundtrip -- and.v`
Also, take a look at some of the [tests](https://github.com/matth2k/nl-compiler/blob/main/tests/verilog.rs):
```rust
#[test]
fn mux_lut() {
let src = "module lut_test (
a,
b,
c,
y
);
input a;
wire a;
input b;
wire b;
input c;
wire c;
output y;
wire y;
LUT3 #(
.INIT(8'b11001010)
) _0_ (
.I0(a),
.I1(b),
.I2(c),
.O(y)
);
endmodule
"
.to_string();
assert_verilog_eq!(src, roundtrip(&src).unwrap());
}
```