https://github.com/mattiamtzlr/epfl-cs173

Everything related to EPFL CS-173: Fundamentals of digital systems
https://github.com/mattiamtzlr/epfl-cs173

course-material university

Last synced: 3 months ago
JSON representation

Everything related to EPFL CS-173: Fundamentals of digital systems

• Host: GitHub
• URL: https://github.com/mattiamtzlr/epfl-cs173
• Owner: mattiamtzlr
• License: cc-by-sa-4.0
• Created: 2024-03-11T15:39:35.000Z (over 2 years ago)
• Default Branch: master
• Last Pushed: 2024-11-10T10:42:52.000Z (over 1 year ago)
• Last Synced: 2025-03-16T08:46:14.509Z (over 1 year ago)
• Topics: course-material, university
• Language: Verilog
• Homepage:
• Size: 7.19 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

README

          
# EPFL CS-173

Everything related to the EPFL CS-173 Fundamentals of digital systems course.  

The two PDFs [CS-173 Exercises-Book](<./CS-173 Exercises-Book.pdf>) and [RV32I Reference Card](<./RV32I Reference Card.pdf>) have **not** been created by me but by the course team.

## Content

- [LogiSim](./LogiSim/) - Logic Circuit modeling using [Logisim-evolution](https://github.com/logisim-evolution/logisim-evolution)

- [Verilog](./Verilog/) - Hardware description using the [Icarus Verilog](https://github.com/steveicarus/iverilog) compilation system.

- [RISC-V](./RISC-V/) - RV32I ISA Assembly for the RISC-V architecture. Interpreted using [Venus](https://inst.eecs.berkeley.edu/~cs61c/fa21/resources/venus-reference/)