https://github.com/maxxsoft/frenda

Split large FIRRTL into separated modules for incremental compilation.
https://github.com/maxxsoft/frenda

chisel compiler firrtl hardware incremental-compilation

Last synced: 7 months ago
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Split large FIRRTL into separated modules for incremental compilation.

• Host: GitHub
• URL: https://github.com/maxxsoft/frenda
• Owner: MaxXSoft
• License: gpl-3.0
• Created: 2021-11-20T11:54:54.000Z (almost 4 years ago)
• Default Branch: master
• Last Pushed: 2021-12-16T01:27:41.000Z (almost 4 years ago)
• Last Synced: 2023-10-20T21:42:53.795Z (about 2 years ago)
• Topics: chisel, compiler, firrtl, hardware, incremental-compilation
• Language: Scala
• Homepage:
• Size: 113 KB
• Stars: 8
• Watchers: 2
• Forks: 1
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • Changelog: CHANGELOG.md
  • License: LICENSE

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README

          
# Frenda

Compile large FIRRTL files incrementally.

## Getting Started

Frenda is a tool for incremental compilation of FIRRTL. It can split FIRRTL into modules, and then compile all the modules incrementally.

For building and using Frenda, you can run the following command lines:

```sh

# build Frenda

sbt assembly

# show help messages

utils/bin/frenda --help

# compile FIRRTL into Verilog files

utils/bin/frenda -i input.fir -td output_dir

```

## Pros and Cons

Frenda can effectively reduce the compilation time of FIRRTL. but at the cost that Frenda cannot do cross-module optimization for the input circuit, such as global DCE.

## Changelog

See [CHANGELOG.md](CHANGELOG.md).

## Copyright and License

Copyright (C) 2010-2021 MaxXing. License GPLv3.