https://github.com/maze1377/pipeline-mips-verilog

A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall
https://github.com/maze1377/pipeline-mips-verilog

control-hazards data-hazards mips mips-architecture mips-instruction mips32 pipeline-mips-verilog pipline verilog

Last synced: 6 months ago
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A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall

• Host: GitHub
• URL: https://github.com/maze1377/pipeline-mips-verilog
• Owner: maze1377
• Created: 2019-07-06T12:49:22.000Z (about 7 years ago)
• Default Branch: master
• Last Pushed: 2025-01-28T19:47:45.000Z (over 1 year ago)
• Last Synced: 2025-06-10T21:10:33.864Z (about 1 year ago)
• Topics: control-hazards, data-hazards, mips, mips-architecture, mips-instruction, mips32, pipeline-mips-verilog, pipline, verilog
• Language: Verilog
• Homepage:
• Size: 229 KB
• Stars: 49
• Watchers: 2
• Forks: 8
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

          

# MIPS pipline

A classic 5-stage pipeline MIPS 32-bit processor.

five stages of a microprocessor: instruction fetch (IF),

instruction decode (ID), execution(EX),

memory access and write (MEM) e write back (WB).

#name of wire and guideline		

![wirename](https://github.com/maze1377/pipeline-mips-verilog/blob/master/screenshots/guidline.jpg)

#states

![state](https://github.com/maze1377/pipeline-mips-verilog/blob/master/screenshots/state.png)

support most of MIPS instruction and solve every hazard with stall.(Data Hazards and Control Hazards) Verilog code.

Developed during the winter 2019 Computer Architecture Laboratory course at the University of Ferdowsi Mashhad.

# Modular design

code start from mypip

other modular named same to original model