https://github.com/mcquerol/memory-cell-vhdl

https://github.com/mcquerol/memory-cell-vhdl

digital-logic flip-flops logisim memory-cell-single-bit vhdl

Last synced: 6 days ago
JSON representation

• Host: GitHub
• URL: https://github.com/mcquerol/memory-cell-vhdl
• Owner: mcquerol
• License: mit
• Created: 2023-08-16T08:56:38.000Z (over 1 year ago)
• Default Branch: main
• Last Pushed: 2024-08-23T17:42:20.000Z (3 months ago)
• Last Synced: 2024-08-23T19:32:09.239Z (3 months ago)
• Topics: digital-logic, flip-flops, logisim, memory-cell-single-bit, vhdl
• Language: VHDL
• Size: 43 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# memory_cell_vhdl

This one bit memory cell is just a D flip flop with a Write Enable (WE), Output Enable (OE) and the data in (D) clock (CLK) and RESET from a D flip Flop

The output Q of the D flip flop goes into a tristate buffer which is the data that is outputted outside of the memory cell. The tristate buffer is enabled by the OE.

This design shows the logic for 1 bit but the vhdl code can be implemented with a structural design to combine multiple of the entities to form e.g. an 8 bit shift register: The output of one block is the input of another and all the WE, OE are connected together