https://github.com/mcquerol/vhdl-projects

VHDL projects for combinational and sequential logic design on FPGA.
https://github.com/mcquerol/vhdl-projects

combinational-logic flip-flops latches logisim memory sequential-logic vhdl

Last synced: 3 months ago
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VHDL projects for combinational and sequential logic design on FPGA.

• Host: GitHub
• URL: https://github.com/mcquerol/vhdl-projects
• Owner: mcquerol
• License: mit
• Created: 2023-08-26T17:06:55.000Z (almost 3 years ago)
• Default Branch: main
• Last Pushed: 2024-12-18T01:22:36.000Z (over 1 year ago)
• Last Synced: 2025-07-12T01:32:55.525Z (11 months ago)
• Topics: combinational-logic, flip-flops, latches, logisim, memory, sequential-logic, vhdl
• Language: VHDL
• Size: 169 KB
• Stars: 2
• Watchers: 1
• Forks: 0
• Open Issues: 2
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

          
# vhdl-projects

This is a standard README file for the vhdl-projects repository.