https://github.com/meiniki/rv32i_sc_logisim
A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.
https://github.com/meiniki/rv32i_sc_logisim
computer-science digital-design educational logisim logisim-evolution processor-architecture risc-v
Last synced: 5 months ago
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A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.
- Host: GitHub
- URL: https://github.com/meiniki/rv32i_sc_logisim
- Owner: meiniKi
- License: mit
- Created: 2022-07-20T09:45:17.000Z (almost 4 years ago)
- Default Branch: main
- Last Pushed: 2023-05-17T21:51:07.000Z (about 3 years ago)
- Last Synced: 2025-01-23T01:14:44.864Z (over 1 year ago)
- Topics: computer-science, digital-design, educational, logisim, logisim-evolution, processor-architecture, risc-v
- Language: Verilog
- Homepage:
- Size: 707 KB
- Stars: 3
- Watchers: 3
- Forks: 0
- Open Issues: 0