https://github.com/melchisedech333/verilog-experiments
:space_invader: My studies with Verilog and notions of digital systems.
https://github.com/melchisedech333/verilog-experiments
digital-system-design digital-systems digital-systems-design digital-systems-fundamentals hdl icarus-verilog verilog verilog-code verilog-examples verilog-hdl verilog-project
Last synced: 2 months ago
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:space_invader: My studies with Verilog and notions of digital systems.
- Host: GitHub
- URL: https://github.com/melchisedech333/verilog-experiments
- Owner: melchisedech333
- License: bsd-3-clause
- Created: 2022-11-01T16:55:55.000Z (over 2 years ago)
- Default Branch: main
- Last Pushed: 2022-11-02T00:49:54.000Z (over 2 years ago)
- Last Synced: 2025-02-03T10:33:37.877Z (4 months ago)
- Topics: digital-system-design, digital-systems, digital-systems-design, digital-systems-fundamentals, hdl, icarus-verilog, verilog, verilog-code, verilog-examples, verilog-hdl, verilog-project
- Language: Verilog
- Homepage:
- Size: 391 KB
- Stars: 1
- Watchers: 2
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: readme.md
- License: license
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README
# Verilog Experiments
Here are some of my studies that I carry out using the Verilog language.
**If my code has helped you, please consider [sponsoring me](https://github.com/sponsors/melchisedech333) :blue_heart:**
:smiley: Author
---
Sponsor: [melchisedech333](https://github.com/sponsors/melchisedech333)
Twitter: [Melchisedech333](https://twitter.com/Melchisedech333)
LinkedIn: [Melchisedech Rex](https://www.linkedin.com/in/melchisedech-rex-724152235/)
Blog: [melchisedech333.github.io](https://melchisedech333.github.io/)
:scroll: License
---
[ BSD-3-Clause license](./license)
## Remember to give me
a beautiful little star :star_struck: