https://github.com/melvinmo/hdl_course_archive
This repository houses my work from the undergraduate hardware description language course in Verilog and the utilization of tools such as ModelSim and Xilinx ISE.
https://github.com/melvinmo/hdl_course_archive
fpga modelsim verilog-hdl xilinx-ise
Last synced: 4 months ago
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This repository houses my work from the undergraduate hardware description language course in Verilog and the utilization of tools such as ModelSim and Xilinx ISE.
- Host: GitHub
- URL: https://github.com/melvinmo/hdl_course_archive
- Owner: MelvinMo
- Created: 2023-08-30T05:27:29.000Z (almost 3 years ago)
- Default Branch: main
- Last Pushed: 2023-08-30T06:11:16.000Z (almost 3 years ago)
- Last Synced: 2025-01-07T15:16:59.328Z (over 1 year ago)
- Topics: fpga, modelsim, verilog-hdl, xilinx-ise
- Language: Verilog
- Homepage:
- Size: 2.21 MB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# HDL_Archive
This repository houses my works from the undergraduate hardware description language course, demonstrating proficiency in Verilog and utilization of industry-standard tools such as ModelSim and Xilinx ISE.
## Assignment 1
This assignment involved designing and testing a sequential logic circuit using Verilog HDL. The objective was to gain hands-on experience in digital circuit design, Verilog modeling, and functional verification using ModelSim.
## Assignment 2
The goal was to enhance skills in structural modeling and test bench automation. I designed a 4-bit binary comparator in Verilog, created a structured test bench with predefined cases, and analyzed the simulation results. This assignment explored advanced Verilog concepts and complex digital design validation.
## Assignment 3
I developed a vending machine controller using the Spartan-6 FPGA in Xilinx ISE. The assignment focused on synthesizable finite state machine (FSM) designs. I coded and simulated the FSM module in Verilog, validating the design on the FPGA.
## Assignment 4
The final assignment involved designing and implementing a 4-bit biquadratic filter algorithm on an FPGA. I optimized the design for speed and analyzed resource utilization and timing. Concepts covered included RTL code development, floating-point to fixed-point conversion, and FPGA optimizations.