https://github.com/mightlaus/cla-full-adder
A high-performance and versatile carry-lookahead (CLA) full adder designed for rapid addition of arbitrary x^y bit inputs.
https://github.com/mightlaus/cla-full-adder
adder digital-circuits high-performance verilog
Last synced: 14 days ago
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A high-performance and versatile carry-lookahead (CLA) full adder designed for rapid addition of arbitrary x^y bit inputs.
- Host: GitHub
- URL: https://github.com/mightlaus/cla-full-adder
- Owner: Mightlaus
- License: gpl-3.0
- Created: 2023-12-16T07:25:09.000Z (about 2 years ago)
- Default Branch: main
- Last Pushed: 2023-12-16T07:35:53.000Z (about 2 years ago)
- Last Synced: 2023-12-16T08:45:56.560Z (about 2 years ago)
- Topics: adder, digital-circuits, high-performance, verilog
- Language: Verilog
- Homepage:
- Size: 18.6 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# CLA-full-adder
A high-performance and versatile carry-lookahead (CLA) full adder designed for rapid addition of arbitrary x^y bit inputs.
## Module Hierarchy
The project follows a modular structure, as illustrated below:
```
Hierarchy
( 1) └── fadd_tb.v
( 2) └── fadd.v
( 3) ├── Sum.v
( 4) ├── CLA.v
( 5) │ ├── CLA*.v
( 6) │ ├── CarryGen.v
( 7) │ └── PGxGen.v
( 8) └── PGGen.v
* denotes a recursive implementation
```
- **fadd_tb.v**: The testbench for the full adder module.
- **fadd.v**: The full adder module that orchestrates the addition process.
- **Sum.v**: Module responsible for calculating the sum of the inputs.
- **CLA.v**: Core carry-lookahead module.
- **PGxGen.v**: Module responsible for generating propagate (P) and generate (G) signals across recursive levels.
- **PGGen.v**: Module for generating propagate (P) and generate (G) signals of inputs.
- **CarryGen.v**: Module for generating carry bits based on propagate (P) and generate (G) signals.