https://github.com/mongshil553/digital-engineering-verilog-assignments

Sophomore 2021 1st Semester Digital Engineering Verilog Assignments
https://github.com/mongshil553/digital-engineering-verilog-assignments

fpga-programming verilog xilinx-vivado

Last synced: about 2 months ago
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Sophomore 2021 1st Semester Digital Engineering Verilog Assignments

• Host: GitHub
• URL: https://github.com/mongshil553/digital-engineering-verilog-assignments
• Owner: mongshil553
• Created: 2024-07-23T04:52:28.000Z (6 months ago)
• Default Branch: main
• Last Pushed: 2024-08-24T02:31:18.000Z (5 months ago)
• Last Synced: 2024-08-24T03:31:47.697Z (5 months ago)
• Topics: fpga-programming, verilog, xilinx-vivado
• Language: Verilog
• Homepage:
• Size: 4.88 KB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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# Verilog-Assignments

Sophomore 2021 1st Semester Digital Engineering Verilog Assignments