https://github.com/mongshil553/digital-engineering-verilog-assignments
Sophomore 2021 1st Semester Digital Engineering Verilog Assignments
https://github.com/mongshil553/digital-engineering-verilog-assignments
fpga-programming verilog xilinx-vivado
Last synced: 3 months ago
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Sophomore 2021 1st Semester Digital Engineering Verilog Assignments
- Host: GitHub
- URL: https://github.com/mongshil553/digital-engineering-verilog-assignments
- Owner: mongshil553
- Created: 2024-07-23T04:52:28.000Z (almost 2 years ago)
- Default Branch: main
- Last Pushed: 2024-08-24T02:31:18.000Z (almost 2 years ago)
- Last Synced: 2025-03-03T02:44:42.192Z (over 1 year ago)
- Topics: fpga-programming, verilog, xilinx-vivado
- Language: Verilog
- Homepage:
- Size: 4.88 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# Verilog-Assignments
Sophomore 2021 1st Semester Digital Engineering Verilog Assignments