https://github.com/mrlsd/fpga
Research & Development FPGA projects for different boards
https://github.com/mrlsd/fpga
altera-fpga fpga sipeed-tang-nano-9k systemverilog verilog
Last synced: about 2 months ago
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Research & Development FPGA projects for different boards
- Host: GitHub
- URL: https://github.com/mrlsd/fpga
- Owner: mrLSD
- License: mit
- Created: 2017-11-15T12:30:15.000Z (over 7 years ago)
- Default Branch: master
- Last Pushed: 2023-10-01T19:07:47.000Z (over 1 year ago)
- Last Synced: 2025-01-06T14:42:50.708Z (4 months ago)
- Topics: altera-fpga, fpga, sipeed-tang-nano-9k, systemverilog, verilog
- Language: GLSL
- Homepage:
- Size: 420 KB
- Stars: 7
- Watchers: 3
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
# FPGA Research & Development
## Supported boards
- Altera devboard Cyclone IV E - `EP4CE10E22C8`
- Sipeed TangNano 9k
## Sipeed TangNano 9k
- Usefull getting started guides:
- Sipeed [website]()
- [Lushat Labs articles](https://learn.lushaylabs.com/getting-setup-with-the-tang-nano-9k/#creating-a-new-project)
- github examples:
- https://github.com/lushaylabs/tangnano9k-series-examples
- https://github.com/sipeed/TangNano-9K-example
- required: [OSS Cad Suite](https://github.com/YosysHQ/oss-cad-suite-build) or just install [Gowin EDA](https://www.gowinsemi.com/en/support/download_eda/).
### Altera Devboard
- Devboard: `Cyclone IV E EP4CE10E22C8`
- Quartus CAD required
FPGA project mostly base on Verilog or SystemVerilog. And implemented for Altera DevelopmentBoard with Quartus CAD.
#### Altera based projects
* **VGA** - output via VGA interfact to motinors. Can draw multy line text with specific fonts.
* **led4_highreg** - 12 LED circle sequence
* **timer** - onboard digital LED count down timer with ability set timer time.
Digital LED and Keys used for I/O.
### LICENSE MIT