https://github.com/mrlsd/mips-one-stage-cpu
MIPS 32 one stage CPU with limited ISA
https://github.com/mrlsd/mips-one-stage-cpu
Last synced: 11 months ago
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MIPS 32 one stage CPU with limited ISA
- Host: GitHub
- URL: https://github.com/mrlsd/mips-one-stage-cpu
- Owner: mrLSD
- License: mit
- Created: 2019-07-16T20:35:13.000Z (over 6 years ago)
- Default Branch: master
- Last Pushed: 2019-07-16T20:43:17.000Z (over 6 years ago)
- Last Synced: 2025-01-06T14:42:39.304Z (about 1 year ago)
- Language: Verilog
- Size: 3.91 KB
- Stars: 1
- Watchers: 2
- Forks: 1
- Open Issues: 0
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Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# MIPS 32 limited ISA CPU
MIPS 32 1-stage CPU with limited ISA. Learning path for limited MIPS architecture.
*Current supported opcodes*:
* LW
LICENSE: MIT