https://github.com/mshr-h/fibonacci_verilog
fibonacci number calculator written in Verilog-HDL
https://github.com/mshr-h/fibonacci_verilog
altera fibonacci fibonacci-numbers iverilog verilog-hdl
Last synced: 4 months ago
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fibonacci number calculator written in Verilog-HDL
- Host: GitHub
- URL: https://github.com/mshr-h/fibonacci_verilog
- Owner: mshr-h
- License: mit
- Created: 2017-02-19T03:35:04.000Z (over 8 years ago)
- Default Branch: master
- Last Pushed: 2017-02-23T12:20:52.000Z (over 8 years ago)
- Last Synced: 2025-06-25T23:02:55.570Z (4 months ago)
- Topics: altera, fibonacci, fibonacci-numbers, iverilog, verilog-hdl
- Language: Verilog
- Size: 41 KB
- Stars: 4
- Watchers: 2
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# Fibonacci number calculator in Verilog-HDL
This is a hardware implemetation of [Fibonacci number](https://en.wikipedia.org/wiki/Fibonacci_number) calculator written in Verilog-HDL.
It supports req/ack handshake protocol.
I've tested on MU500-RX and DE1-SoC fpga board.
## Required Tools
- [Icarus Verilog(>=10.0)](http://iverilog.wikia.com/wiki/Installation_Guide)
- [Altera Quartus Prime(>=15.0)](https://www.altera.co.jp/downloads/download-center.html)
## Timing chart
66th Fibonacci number is `27777890035288`.
## Source Code Organization
The source code is organized as follows:
```text
docs/ documentation
fpga/ fpga related files
rtl/ RTL files for Motion Estimation Processor
testbench/ test suites
```
## Port declaration
| Port name | IO | Description |
| :------- | :----: | :----------------------- |
| rst\_n | input | low active reset |
| clk | input | clock signal |
| req | input | request for handshake |
| n | input | N'th fibonacci number |
| ack | output | acknowledge for handshake |
| result | output | fibonacci number |
## Parameters
| Name | Description |
| :----- | :------------------------ |
| N\_IN | bit width of input number |
| N\_OUT | bit width of output number |