https://github.com/muhammadtalhasami/rv32i_single_cycle

This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.
https://github.com/muhammadtalhasami/rv32i_single_cycle

fetch-stage-pipeline gtkwave hardware-designs muhammadtalhasami-github- pipeline-processor risc-v-assembly risc-v-pipeline risc-v-processor risc-v-processor-images rv32i rv32i-processor single-cycle-processor single-cycle-processor-gtkwave-image system-verilog system-verilog-codes verilator verilog verilog-code-examples verilog-codes vhdl

Last synced: 9 days ago
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This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.

• Host: GitHub
• URL: https://github.com/muhammadtalhasami/rv32i_single_cycle
• Owner: muhammadtalhasami
• Created: 2023-10-19T11:54:35.000Z (about 1 year ago)
• Default Branch: main
• Last Pushed: 2024-08-10T19:57:37.000Z (5 months ago)
• Last Synced: 2024-11-06T10:13:45.943Z (about 2 months ago)
• Topics: fetch-stage-pipeline, gtkwave, hardware-designs, muhammadtalhasami-github-, pipeline-processor, risc-v-assembly, risc-v-pipeline, risc-v-processor, risc-v-processor-images, rv32i, rv32i-processor, single-cycle-processor, single-cycle-processor-gtkwave-image, system-verilog, system-verilog-codes, verilator, verilog, verilog-code-examples, verilog-codes, vhdl
• Language: Verilog
• Homepage:
• Size: 168 KB
• Stars: 3
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
## RV32I Single Cycle and Fetch Pipeline Processor Implementations

This repository contains implementations of processors based on the RV32I instruction set architecture using Verilog HDL: a single-cycle processor and a fetch pipeline processor.