https://github.com/muhammadtalhasami/verilog_practice
Verilog is a hardware description language. This repo is basically a learning journey of verilog
https://github.com/muhammadtalhasami/verilog_practice
design gtkwave hardware-designs testbench verilog- vhdl
Last synced: 5 months ago
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Verilog is a hardware description language. This repo is basically a learning journey of verilog
- Host: GitHub
- URL: https://github.com/muhammadtalhasami/verilog_practice
- Owner: muhammadtalhasami
- Created: 2023-08-07T10:04:14.000Z (about 2 years ago)
- Default Branch: master
- Last Pushed: 2023-08-21T07:16:33.000Z (about 2 years ago)
- Last Synced: 2025-05-11T00:59:16.630Z (5 months ago)
- Topics: design, gtkwave, hardware-designs, testbench, verilog-, vhdl
- Language: Verilog
- Homepage:
- Size: 5.86 KB
- Stars: 1
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files: