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https://github.com/nishit0072e/2bit-comparator
2 bit comparator design in transistor level in eSim software foremerly FreeCAD
https://github.com/nishit0072e/2bit-comparator
Last synced: 4 days ago
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2 bit comparator design in transistor level in eSim software foremerly FreeCAD
- Host: GitHub
- URL: https://github.com/nishit0072e/2bit-comparator
- Owner: nishit0072e
- Created: 2024-12-05T16:14:14.000Z (about 1 month ago)
- Default Branch: main
- Last Pushed: 2024-12-05T16:22:30.000Z (about 1 month ago)
- Last Synced: 2024-12-05T17:24:04.757Z (about 1 month ago)
- Language: TL-Verilog
- Size: 373 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# 2-bitcomparator_mixedsignal_esim_SKY130
## Contents
- [Abstract](#abstract)
- [Circuit Details](#circuit-details)
- [Truth Table](#truth-table)
- [Software Used](#software-used)
- [Steps to run generate NgVeri Model](#steps-to-run-generate-ngveri-model)
## Abstract
A Comparator is a combinational
circuit that compares two binary numbers in order to find
out whether one binary number is equal, less than, or
greater than the other binary number. The Circuit will have two inputs one for A and the other for B and have three output terminals,
one for A > B condition,
one for A = B condition, and one for A
The digital portion of the circuit is implemented using Verilog.
For the analog portion, the two 3-input ”OR” gates and one 2-input ”AND” gate are replaced with NMOS and
PMOS transistors, making the circuit mixed-signal.
The output of the mixed signal 2-bit comparator
circuit may be less than, equal to (ET), or greater than.
## Truth Table
| Input A1 | Input A0 | Input B1 | Input B0 | Output AB |
| ------------- | ------------- | ------------- | ------------- | ------------- | ------------- | ------------- |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| 0 | 0 | 0 | 1 | 1 | 0 | 0 |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 |
| 0 | 0 | 1 | 1 | 1 | 0 | 0 |
| 0 | 1 | 0 | 0 | 0 | 0 | 1 |
| 0 | 1 | 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 | 1 | 0 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 1 | 1 | 0 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 1 |
| 1 | 1 | 0 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 0 | 0 | 0 | 1 |
| 1 | 1 | 1 | 0 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 0 | 1 | 0 |
## Software Used
### eSim 2.3
It is an Open Source EDA developed by FOSSEE, IIT Bombay. It is used for electronic circuit simulation. It is made by the combination of two software namely NgSpice and KiCAD.
For more details refer:
https://esim.fossee.in/home
### NgSpice
It is an Open Source Software for Spice Simulations. For more details refer:
http://ngspice.sourceforge.net/docs.html
### Makerchip
It is an Online Web Browser IDE for Verilog/System-verilog/TL-Verilog Simulation. Refer
https://www.makerchip.com/
## Circuit Diagram in eSim
The following is the schematic in eSim:
## Steps to run generate NgVeri Model
1. Open eSim
2. Run NgVeri-Makerchip
3. Add top level verilog file in Makerchip Tab
4. Click on NgVeri tab
5. Add dependency files
6. Click on Run Verilog to NgSpice Converter
7. Debug if any errors
8. Model created successfully