https://github.com/oddball/ipxact2systemverilog
Translates IPXACT XML to synthesizable VHDL or SystemVerilog
https://github.com/oddball/ipxact2systemverilog
ip-xact systemverilog verilog vhdl
Last synced: 10 months ago
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Translates IPXACT XML to synthesizable VHDL or SystemVerilog
- Host: GitHub
- URL: https://github.com/oddball/ipxact2systemverilog
- Owner: oddball
- License: gpl-2.0
- Created: 2013-09-14T17:45:45.000Z (almost 13 years ago)
- Default Branch: master
- Last Pushed: 2025-08-28T18:11:05.000Z (10 months ago)
- Last Synced: 2025-08-28T23:55:34.284Z (10 months ago)
- Topics: ip-xact, systemverilog, verilog, vhdl
- Language: Python
- Homepage:
- Size: 4.78 MB
- Stars: 63
- Watchers: 13
- Forks: 21
- Open Issues: 5
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
# ipxact2systemverilog ipxact2rst ipxact2md ipxact2vhdl ipxact2c
[](https://github.com/oddball/ipxact2systemverilog/actions/workflows/ci.yml)
[](https://pypi.python.org/pypi/ipxact2systemverilog/)
This software takes an IP-XACT description of register banks, and
generates synthesizable VHDL and SystemVerilog packages and
ReStructuredText documents. It ONLY considers register bank
descriptions. The software does not generate OVM or UVM test bench
packages. In the example/tb directory there is an example of how to use
the generated packages.
## Usage
```bash
pip install ipxact2systemverilog
ipxact2systemverilog --srcFile FILE --destDir DIR
ipxact2rst --srcFile FILE --destDir DIR
ipxact2md --srcFile FILE --destDir DIR
ipxact2vhdl --srcFile FILE --destDir DIR
ipxact2c --srcFile FILE --destDir DIR
```
## Development
See https://github.com/oddball/ipxact2systemverilog
```bash
python -m venv venv
source venv/bin/activate
pip install build
python -m build
python -m pip install .
# In order to publish:
pip install twine
twine upload dist/*
```
## Testing the example file
```bash
make
```
If Modelsim is installed: :
```bash
make compile
make sim
```
## Note
You can use to convert to almost any
fileformat.
## Validation
To validate your xml :
```bash
xmllint --noout --schema ipxact2systemverilog/xml/component.xsd example/input/test.xml
```
## Dependencies
```bash
pip install docutils lxml mdutils
```
## Dependencies used by makefile
These are not needed for ipxact2systemverilog, but used for generating
some of the files in example/output. Instructions are for MacOsX, similiar packages are
available for Linux and Windows.
```bash
brew install pandoc
# if you want to use sphinx
brew install texlive
sudo tlmgr install latexmk
```
## TODO
- A better test bench for the generated packages should be implemented.
- More complicated IPXACT files should be added and tried out.
- Add support for the SystemVerilog generator to have a register field
of an enumerated type.
- Support DIM
- Eat some cheese and drink some wine 2024-06-20