https://github.com/openhwgroup/core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.
https://github.com/openhwgroup/core-v-verif

risc-v systemverilog uvm verification

Last synced: about 19 hours ago
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Functional verification project for the CORE-V family of RISC-V cores.

• Host: GitHub
• URL: https://github.com/openhwgroup/core-v-verif
• Owner: openhwgroup
• License: other
• Created: 2019-11-29T16:09:33.000Z (almost 5 years ago)
• Default Branch: master
• Last Pushed: 2024-10-29T13:04:43.000Z (5 days ago)
• Last Synced: 2024-10-29T15:56:08.677Z (5 days ago)
• Topics: risc-v, systemverilog, uvm, verification
• Language: Assembly
• Homepage: https://docs.openhwgroup.org/projects/core-v-verif/en/latest/index.html
• Size: 112 MB
• Stars: 443
• Watchers: 48
• Forks: 221
• Open Issues: 133
• Metadata Files:
  • Readme: README.md
  • Contributing: CONTRIBUTING.md
  • License: LICENSE.md
  • Code of conduct: CODE_OF_CONDUCT.md

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README

        


# core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

## Getting Started

First, have a look at the [OpenHW Group's website](https://www.openhwgroup.org) to learn a bit more about who we are and what we are doing.




For first time users of CORE-V-VERIF, the **Quick Start Guide** in the [CORE-V-VERIF Verification Strategy](https://docs.openhwgroup.org/projects/core-v-verif/en/latest/quick_start.html) is the best place to start.

## Directory Structure of this Repo

### bin

Various utilities for running tests and performing various verification-related activities in the core-v-verif repository.

### core-v-cores

Empty sub-directory into which the RTL from one or more of the [CORE-V-CORES](https://github.com/openhwgroup/core-v-cores) repositories is cloned.

### cv32e40p, cv32e40x, cv32e40s, cva6

Core-specific verification code.

### docs

Sources for the Verification Strategy document, DV plans, coding style guidelines and available coverage reports.

### mk

Common simulation Makefiles that support testbenches for all CORE-V cores.

### lib

Common components for the all CORE-V verification environments.

### vendor_lib

Verification components supported by third-parties.

## Contributing

We highly appreciate community contributions. You can get a sense of our current needs by reviewing the GitHub

[projects](https://github.com/openhwgroup/core-v-verif/projects) associated with this repository.   Individual work-items

within a project are defined as [issues](https://github.com/openhwgroup/core-v-verif/issues) with a `task` label.



To ease our work of reviewing your contributions, please:

* Review [CONTRIBUTING](https://github.com/openhwgroup/core-v-verif/blob/master/CONTRIBUTING.md)

and our [SV/UVM coding style guidelines](https://github.com/openhwgroup/core-v-verif/blob/master/docs/CodingStyleGuidelines.md).

* Split large contributions into smaller commits addressing individual changes or bug fixes.

Do not mix unrelated changes into the same commit!

* Write meaningful commit messages.

* If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.

## Acknowledgements

Check out the [acknowledgements](ACKNOWLEDGEMENTS.md).