https://github.com/ovuiproduction/operating-system-simulator
The OS Simulator replicates key functionalities like memory management, CPU scheduling, and interrupts. It evolves from single-program execution to multi-programming with virtual memory, implementing scheduling algorithms, page replacement, and a page table register.
https://github.com/ovuiproduction/operating-system-simulator
cpp cpu-scheduling interrupt-handling operating-system os-simulator page-replacement-algorithm process-management virtual-memory
Last synced: 17 days ago
JSON representation
The OS Simulator replicates key functionalities like memory management, CPU scheduling, and interrupts. It evolves from single-program execution to multi-programming with virtual memory, implementing scheduling algorithms, page replacement, and a page table register.
- Host: GitHub
- URL: https://github.com/ovuiproduction/operating-system-simulator
- Owner: ovuiproduction
- License: mit
- Created: 2024-03-26T20:04:55.000Z (about 2 years ago)
- Default Branch: main
- Last Pushed: 2025-08-06T19:51:30.000Z (10 months ago)
- Last Synced: 2025-08-06T21:35:09.029Z (10 months ago)
- Topics: cpp, cpu-scheduling, interrupt-handling, operating-system, os-simulator, page-replacement-algorithm, process-management, virtual-memory
- Language: C++
- Homepage: https://github.com/ovuiproduction/Operating-System-Simulator
- Size: 42 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
Awesome Lists containing this project
README
# Operating System Simulator
## Simulation of Operating System fuctionality such as
1. Memory Managment
2. Virtual Memory
3. Process Execution
4. Process Scheduling
5. Interuppt Handling
## Phase - 1
### Problem Statement :
1. CPU / Machine Simulation
2. Supervisor Call through interrupt
### Assumption :
1. Jobs entered without error in input file
2. No physical separation between jobs
3. Job outputs separated in output file by 2 blank lines
4. Program loaded in memory starting at location 00
5. No multiprogramming, load and run one program at a time
6. SI interrupts for service request
### NOTATION
M: memory;
IR: Instruction Register (4 bytes)
IR [1, 2]: Bytes 1, 2 of IR/Operation Code
IR [3, 4]: Bytes 3,4 of IR/Operand Address
M [&]: Content of memory location
IC: Instruction Counter Register (2 bytes)
R: General Purpose Register (4 bytes)
C: Toggle (1 byte)
## Phase - 2
### Problem Statement :
1. CPU / Machine Simulation
2. Supervisor Call through interrupt
3. Multiple-Program execution
4. Error handling in jobs
5. Handling Program interrupt,Timing interrupt and system interrupt
### ASSUMPTIONS:
1. Jobs may have program errors
2. PI interrupt for program errors introduced
3. No physical separation between jobs
4. Job outputs separated in output file by 2 blank lines
5. Paging introduced, page table stored in real memory
6. Program pages allocated one of 30 memory block using random number generator
7. Load and run one program at a time
8. Time limit, line limit, out-of-data errors introduced
9. TI interrupt for time-out error introduced
10. 2-line messages printed at termination
### NOTATION
M: memory
IR: Instruction Register (4 bytes)
IR [1,2]: Bytes 1,2 of IR/Operation Code
IR [3, 4]: Bytes 3, 4 of IR/Operand Address
M[&]: Content of memory location
IC: Instruction Counter Register (2 bytes)
R: General Purpose Register (4 bytes)
C: Toggle (1 byte)
PTR: Page Table Register (4 bytes)
PCB: Process Control Block (data structure)
VA: Virtual Address
RA: Real Address
TTC: Total Time Counter
LLC: Line Limit Counter
TTL: Total Time Limit
TLL: Total Line Limit
EM: Error Message
## License
This project is licensed under the [MIT License](https://github.com/ovuiproduction/Operating-System-Simulator/blob/main/LICENSE)