https://github.com/paulopacitti/ascon-v

5️⃣ Ascon lightweight cryptographic algorithm implementation for improved performance on riscv64
https://github.com/paulopacitti/ascon-v

allwinner allwinner-d1 ascon cryptography lightweight-cryptography risc-v riscv64

Last synced: 3 months ago
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5️⃣ Ascon lightweight cryptographic algorithm implementation for improved performance on riscv64

• Host: GitHub
• URL: https://github.com/paulopacitti/ascon-v
• Owner: paulopacitti
• License: mit
• Created: 2023-09-09T21:57:46.000Z (over 1 year ago)
• Default Branch: main
• Last Pushed: 2024-02-22T00:27:38.000Z (about 1 year ago)
• Last Synced: 2025-01-16T23:16:01.473Z (4 months ago)
• Topics: allwinner, allwinner-d1, ascon, cryptography, lightweight-cryptography, risc-v, riscv64
• Language: C
• Homepage:
• Size: 11.9 MB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# ascon-v 5️⃣

Ascon lightweight cryptographic algorithm implementation for improved performance on RISC-V. Tested on the Allwinner D1 processor. My bachelor's thesis at [UNICAMP's Institute of Computing](https://ic.unicamp.br/en/).

![](cover.jpg)

## Abstract

> RISC-V is a promising ISA and soon will be the architecture of many chips, specially embedded systems. It's necessary to guarantee that applications that run in systems designed with RISC-V will be at the same time secure and cryptographically fast. The NIST Lightweight Cryptography competition selected the finalist: Ascon, a family of cryptography algorithms designed to run in devices with low computational power. This research explores the Ascon family of algorithms on the RISC-V 64-bit architecture, analysing the Ascon permutation and the Ascon-128 algorithm, and whether it's possible to optimize it for `riscv64`, proposing a new technique regarding the decryption implementation. The implementation developed in this research was benchmarked in the Allwinner D1 chip, a RISC-V 64-bit 1 GHz single-issue CPU supporting the RV64GC ISA, and compared with other implementations. Finally, it's discussed that new microarchitectures, and, the future of the RISC-V ISA with new instructions extensions recently ratified, could improve the performance of the Ascon family of algorithms and other cryptographic algorithms.

## Structure

- `lib/`: libraries

- `ref/`: reference [implementation](https://github.com/ascon/ascon-c)

- `opt64`: implementation optimized for 64-bit architectures, made by the Ascon team.

- `src/`: source code for `ascon-v`, optmized implementation for `rv64imac`

- `benchmark/`: performance benchmark comparing the different implmentations

- `tests/`: tests for `ascon-v`

- `tex/`: source files for TeX used for building the essay PDF. The research paper is written in the `tex/main.pdf` file