https://github.com/pconst/xilinx_max_power

Creating dummy load to dissipate maximum power in Xilinx FPGA
https://github.com/pconst/xilinx_max_power

arty board cooling development digilent fpga power shift-register soc systemverilog test ultrascale verilog xilinx zinq

Last synced: about 1 month ago
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Creating dummy load to dissipate maximum power in Xilinx FPGA

• Host: GitHub
• URL: https://github.com/pconst/xilinx_max_power
• Owner: pConst
• Created: 2018-04-07T22:51:31.000Z (over 6 years ago)
• Default Branch: master
• Last Pushed: 2018-04-08T00:24:04.000Z (over 6 years ago)
• Last Synced: 2023-08-10T19:39:31.724Z (over 1 year ago)
• Topics: arty, board, cooling, development, digilent, fpga, power, shift-register, soc, systemverilog, test, ultrascale, verilog, xilinx, zinq
• Language: SystemVerilog
• Size: 86.9 KB
• Stars: 2
• Watchers: 3
• Forks: 1
• Open Issues: 0

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