https://github.com/perehinik/logic_analyzer_fpga_config

Vivado project for Xilinx Artix FPGA, used in logic analyzer
https://github.com/perehinik/logic_analyzer_fpga_config

fpga verilog vivado xilinx

Last synced: 6 days ago
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Vivado project for Xilinx Artix FPGA, used in logic analyzer

• Host: GitHub
• URL: https://github.com/perehinik/logic_analyzer_fpga_config
• Owner: perehinik
• Created: 2021-01-03T16:21:28.000Z (almost 4 years ago)
• Default Branch: main
• Last Pushed: 2021-07-16T18:21:31.000Z (over 3 years ago)
• Last Synced: 2023-08-03T21:46:37.737Z (over 1 year ago)
• Topics: fpga, verilog, vivado, xilinx
• Language: VHDL
• Homepage:
• Size: 21.5 MB
• Stars: 8
• Watchers: 3
• Forks: 2
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# Logic_Analyzer_FPGA_Config

Vivado project for Xilinx Artix FPGA, used in logic analyzer

Functional diagram:

![Image](images/DIAG.PNG)