https://github.com/portal-co/asm-arch
Assembly target types and data structures
https://github.com/portal-co/asm-arch
aarch64 amd64 armv6 armv7 armv8 assembly compiler riscv rv32 rv32g rv32i rv32im rv64 rv64g rv64i rv64im x64 x86 x86-64
Last synced: 29 days ago
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Assembly target types and data structures
- Host: GitHub
- URL: https://github.com/portal-co/asm-arch
- Owner: portal-co
- Created: 2025-10-22T09:50:26.000Z (8 months ago)
- Default Branch: main
- Last Pushed: 2026-05-14T21:44:19.000Z (about 1 month ago)
- Last Synced: 2026-05-14T23:36:46.312Z (about 1 month ago)
- Topics: aarch64, amd64, armv6, armv7, armv8, assembly, compiler, riscv, rv32, rv32g, rv32i, rv32im, rv64, rv64g, rv64i, rv64im, x64, x86, x86-64
- Language: Rust
- Homepage:
- Size: 382 KB
- Stars: 0
- Watchers: 0
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# asm-arch
Assembly target types and data structures for code generation and manipulation.
## Overview
This workspace provides a collection of crates for working with assembly-level representations and code generation, primarily focused on x86-64 architecture support with extensible semantics and register allocation utilities.
## Crates
Note: The RISC-V crate `portal-solutions-asm-riscv64` includes a robust desugaring wrapper to
handle complex memory addressing and operand materialization. See `crates/asm-riscv64/src/desugar.rs` for details.
Changelog (desugaring improvements):
- Hardened temp selection with optional stack-spill behavior when temps conflict.
- Preserves memory access `MemorySize` and `RegisterClass` across materializations.
- Properly folds large displacements into base registers and avoids mem→mem clobbers.
- Added comprehensive unit tests covering scale factors, large displacements, temp conflicts, and mem→mem cases.
### portal-solutions-asm-x86-64
Core x86-64 assembly types and output generation.
- **Architecture configuration** (`X64Arch`): Configure x86-64 features like APX (Advanced Performance Extensions)
- **Register handling** (`reg`): Register formatting and display with support for different sizes (8/16/32/64-bit)
- **Condition codes** (`ConditionCode`): x86-64 condition codes for conditional instructions
- **Instruction output** (`out`): Traits and implementations for generating assembly output
- `WriterCore`: Core trait for emitting individual instructions
- `Writer`: Extended trait with label support
- Argument types (`arg`): Memory and register operand representations
### portal-solutions-asm-aarch64
AArch64 (ARM64) assembly types and output generation, with x86-64 translation support.
- **Architecture configuration** (`AArch64Arch`): AArch64-specific configuration
- **Register handling** (`reg`): Support for 31 GPRs (X0-X30) plus SP, and 32 SIMD registers (V0-V31)
- **Condition codes** (`ConditionCode`): Complete AArch64 condition code set
- **Instruction output** (`out`): Full instruction generation similar to x86-64
- **x64_shim** (optional): Translation guide for mapping x86-64 instructions to AArch64
- Condition code translation
- Instruction mapping documentation
- Performance notes for complex translations
### portal-solutions-asm-semantics
Semantic representation of assembly operations.
- **Argument kinds** (`ArgKind`, `MemArgKind`): Represent fixed registers, slots, previous values, and literals
- **Semantic trees** (`Semantic`, `PredicateTree`): Represent conditional and computed values
- **Value operations** (`Val`): Binary operations, jumps, dereferences, and control flow
### portal-solutions-asm-regalloc
Register allocation utilities for stack-based virtual machines.
- **Register allocation** (`RegAlloc`): Manage register assignments with stack spilling
- **Frame tracking** (`RegAllocFrame`): Track register states (reserved, empty, stack, local)
- **Commands** (`Cmd`): Push, pop, and local variable operations
## Features
All crates support `no_std` environments. Enable the `alloc` feature for heap allocation support:
```toml
[dependencies]
portal-solutions-asm-x86-64 = { version = "0.1.0", features = ["alloc"] }
portal-solutions-asm-aarch64 = { version = "0.1.0", features = ["alloc", "x64_shim"] }
```
### Feature Flags
- **`alloc`**: Enable heap allocation support (available in all crates)
- **`x64_shim`** (aarch64 only): Enable x86-64 to AArch64 translation utilities
## License
MPL-2.0
## Goals
- [ ] Maintain and expand architecture support (x86-64, AArch64, RISC-V, JVM)
- [ ] Optimize register allocation algorithms
- [ ] Ensure semantic consistency across architectures
## Progress
- [ ] Implemented core support for x86-64 and AArch64
- [ ] Added register allocation and semantic modeling crates
- [ ] RISC-V desugaring improvements (hardened temp selection, large displacement folding)
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