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https://github.com/postspectacular/cmsis-svd-srcgen

Extensible ARM CMSIS SVD spec based, multi-language source code generator
https://github.com/postspectacular/cmsis-svd-srcgen

arm cmsis codegen svd

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Extensible ARM CMSIS SVD spec based, multi-language source code generator

Host: GitHub
URL: https://github.com/postspectacular/cmsis-svd-srcgen
Owner: postspectacular
Created: 2015-12-19T16:06:10.000Z (about 9 years ago)
Default Branch: master
Last Pushed: 2016-01-01T17:48:21.000Z (about 9 years ago)
Last Synced: 2024-10-24T16:29:18.589Z (3 months ago)
Topics: arm, cmsis, codegen, svd
Language: XSLT
Size: 12.7 KB
Stars: 18
Watchers: 7
Forks: 1
Open Issues: 0
Metadata Files:
- Readme: README.org

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README

* cmsis-svd-srcgen

Convert ARM CMSIS SVD specs (processor peripherals, register &
bitfields) into source code for different languages.

Currently supported target languages are: Asm (GCC flavor), C and
Clojure. Other languages can be easily supported by defining a new
XSLT stub file with language specific configuration/formatting.

Project inspired by: [[https://github.com/posborne/cmsis-svd][posborne/cmsis-svd]]

** Usage

#+BEGIN_SRC shell
./convert asm|c|clj svd-file > output-file

# filtered output via "only" and "excl" params
# only includes given peripheral IDs or excludes these
./convert lang svd only=PERIPH1,PERIPH2... > output
./convert lang svd excl=PERIPH1,PERIPH2... > output
#+END_SRC

** Requirements

- [[http://www.saxonica.com/download/opensource.xml][SAXON-HE 9.7+]] (or another XSLT2.0 capable processor)
- Java 7+

You'll also need to download an SVD file for your CPU. A list of SVDs
for all manufacturers is here (under CMSIS-SVD tab on that page,
requires registration):

http://www.arm.com/products/processors/cortex-m/cortex-microcontroller-software-interface-standard.php

STM32 CPU specs can be found here:

https://cmsis.arm.com/vendor/stmicroelectronics/

** Output format

Depending on included details in SVD file, the following definitions
are generated:

- peripheral base registers
- peripheral sub-registers (abs address and offset)
- register reset value
- register bitfield shift offset & mask

Some SVD specs define derived periphals. The extractor supports this
feature and generates a replicated register set (with correct address
offsets) for each derived definition.

*** Naming convention

The overall generate symbol formats follow these patterns (words
prefixed with =$= are variable):

#+BEGIN_SRC
$PERIPHERAL baseaddress
$PERIPHERAL_$REGISTER baseaddress + registeroffset
$PERIPHERAL_$REGISTER_OFFSET registeroffset
$PERIPHERAL_$REGISTER_RESET resetvalue (if given)
$PERIPHERAL_$REGISTER_$FIELD xx (absolute bit mask, e.g. "0xf << 24")
$PERIPHERAL_$REGISTER_$FIELD_SHIFT xx (bit position)
#+END_SRC

Because different symbols are defined for each bitfield item, the
generated files can become quite large (10k+ lines). Use the device
filtering options to reduce file size and only include the ones used
for your project.

*** Example output
**** C

#+BEGIN_SRC c
/****************************************************************
* STM32F401x SVD peripherals & registers
* generated @ 2015-12-23 13:30:59
*
* DO NOT EDIT! This file was autogenerated with:
* http://github.com/postspectacular/cmsis-svd-srcgen
****************************************************************/

#ifndef _CMSIS_SVD_H
#define _CMSIS_SVD_H

/****************************************************************
* General-purpose I/Os (derived from GPIOH)
****************************************************************/
#define GPIOD 0x40020c00
#define GPIOD_MODER (GPIOD + 0x0) // GPIO port mode register
#define GPIOD_MODER_OFFSET 0x0
#define GPIOD_MODER_RESET 0x00000000
#define GPIOD_MODER_MODER15 (0x3 << 30)
#define GPIOD_MODER_MODER15_SHIFT 30
#define GPIOD_MODER_MODER14 (0x3 << 28)
#define GPIOD_MODER_MODER14_SHIFT 28
...

/****************************************************************
* Nested Vectored Interrupt Controller
****************************************************************/
#define NVIC 0xe000e000
#define NVIC_ICTR (NVIC + 0x4) // Interrupt Controller Type Register
#define NVIC_ICTR_OFFSET 0x4
#define NVIC_ICTR_RESET 0x00000000
#define NVIC_ICTR_INTLINESNUM 0xf
#define NVIC_ICTR_INTLINESNUM_SHIFT 0
#define NVIC_STIR (NVIC + 0xf00) // Software Triggered Interrupt Register
#define NVIC_STIR_OFFSET 0xf00
#define NVIC_STIR_RESET 0x00000000
#define NVIC_STIR_INTID 0x1ff
#define NVIC_STIR_INTID_SHIFT 0
...
#+END_SRC

** Contributors

| *Name* | *Role* | *Website* |
|-----------------+---------------------------------+-------------------------------------------|
| [[mailto:[email protected]][Karsten Schmidt]] | initiator & principal developer | http://postspectacular.com, http://thi.ng |

** License