https://github.com/priyanshscpp/ECE907-Single-Port-RAM-VLSI-CourseWork
Single-Port RAM Implementation
https://github.com/priyanshscpp/ECE907-Single-Port-RAM-VLSI-CourseWork
amd64 amdgpu vhdl xilinix
Last synced: 11 months ago
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Single-Port RAM Implementation
- Host: GitHub
- URL: https://github.com/priyanshscpp/ECE907-Single-Port-RAM-VLSI-CourseWork
- Owner: priyanshscpp
- Created: 2024-05-10T18:14:36.000Z (almost 2 years ago)
- Default Branch: main
- Last Pushed: 2024-06-21T10:26:03.000Z (almost 2 years ago)
- Last Synced: 2025-02-26T22:13:56.458Z (about 1 year ago)
- Topics: amd64, amdgpu, vhdl, xilinix
- Language: VHDL
- Homepage:
- Size: 6.84 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# Single-Port RAM Implementation
This repository provides a Verilog implementation of a single-port Random Access Memory (RAM) module. A single-port RAM allows access to one memory location at a time for either reading or writing data.
## Getting Started
Clone the Repository:
Bash
git clone https://github.com/priyanshuhbti/single-port-ram.git
Use code with caution.
content_copy
Synthesis and Simulation (Optional):-
If you intend to synthesize or simulate the RAM design, ensure you have the necessary hardware description language (HDL) tools installed and configured. The specific steps will vary depending on your tools.
## Built With
The single_port_ram.v file will typically contain the following sections:
Parameterization: Allow customization of data and address widths.
Memory Declaration: Create a register array to store the RAM data.
Read Logic: Implement read operation based on the address and enable signals.
Write Logic: Implement write operation based on the address, write enable, and data input signals.
Output Logic: Assign the appropriate data (read or written) to the data_out port.
- [VHDL](https://www.contributor-covenant.org/)
- [Xilinx-AMD](https://creativecommons.org/)