https://github.com/ps2/subg_rfspy_circleci

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Host: GitHub
URL: https://github.com/ps2/subg_rfspy_circleci
Owner: ps2
License: mit
Created: 2018-06-16T20:32:01.000Z (about 8 years ago)
Default Branch: master
Last Pushed: 2018-06-16T20:37:09.000Z (about 8 years ago)
Last Synced: 2025-02-02T05:25:26.475Z (over 1 year ago)
Language: C
Size: 178 KB
Stars: 0
Watchers: 1
Forks: 0
Open Issues: 0
Metadata Files:
- Readme: Readme.md
- License: LICENSE

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README

# subg_rfspy

## Pre-Requisites for Building subg_rfspy

[sdcc] (http://sdcc.sourceforge.net/) package is required for this build.

sudo apt-get install sdcc

It's also possible to build it under Windows. The best way to do this is to:

1. install SDCC
2. install Cygwin
3. use Cygwin to install make
4. Use cygwin bash to build the project

# Building

You'll need to select a build type, like `spi1_alt2`. The examples below use this value, but you'll want to use the correct one for your hardware and use case. See below for different hardware types and use cases.

Perform the build. The output file will be stored at output/uart0_alt1_RILEYLINK_US/uart0_alt1_RILEYLINK_US.hex

make -f Makefile.spi1_alt2

Perform the install:

make -f Makefile.spi1_alt2 install

# Radio Frequency Selection

This code defaults to building firmware that is tuned to 916.5 Mhz. You can also build a 'WorldWide' firmware. This changes the default frequency to 868 and tweaks a few other settings.

make -f Makefile.spi1_alt2 RADIO_LOCALE=WW

# RileyLink

If you are using a [RileyLink](https://github.com/ps2/rileylink) via the onboard bluetooth module (which should be loaded with ble_rfspy), then you'll want to use `spi1_alt2` as your build type.

# Protocol

See [protocol.md](protocol.md)

# Addendum

## Serial/Uart Support

Serial support is no longer supported. See [serial.md](serial.md) for
historical information.

## Frequency Channel Selection

Each channel number corresponds to a different specific frequency. Channels start with 916.5 MHz at
Channel 0 and end with 934.4 MHz at Channel 255, in steps of about 0.07 MHz. You can select different
channels by adjusting the CHANNR.CHAN register. Available channels are governed by the following equation:

`f_carrier = (24MHz/(2^16))*(FREQ + CHAN(256 + CHANSPC_M)*2^(CHANSPC_E - 2))`

The base frequency, FREQ, is set by the FREQ2, FREQ1, and FREQ0 registers. The value default value is
2502768 (0x263070).
CHANSPC_M and CHANSPC_E are used to set the channel spacing, and are contained in the registers MDMCFG0
and MDMCFG1 (bits 1:0), respectively. Their default values are 126 (0x7E) and 1.

## Supported Registers

### SYNC1 (0x00)

Sync Word, High Byte. 8 MSB of 16-bit sync word.

### SYNC0 (0x01)

Sync Word, Low Byte. 8 LSB of 16-bit sync word.

### PKTLEN (0x02)

Packet Length. Indicates the packet length when fixed length packets are enabled. If
variable length packets are used, this value indicates the maximum length
packets allowed.

### PKTCTRL1 (0x03)

Packet Automation Control. Different bit ranges have different functions.
See CC1110/CC1111 datasheet for more information.

### PKTCTRL0 (0x04)

Packet Automation Control. Different bit ranges have different functions.
See CC1110/CC1111 datasheet for more information.

### ADDR (0x05)

Device Address. Address used for packet filtration. Optional broadcast addresses are 0
(0x00) and 255 (0xFF).

### CHANNR (0x06)

Channel Number. The 8-bit unsigned channel number, which is multiplied by the channel
spacing setting and added to the base frequency.

### FSCTRL1 (0x07)

Frequency Synthesizer Control.

### FSCTRL0 (0x08)

Frequency Synthesizer Control. Frequency offset added to the base frequency before being used by the
FS.

### FREQ2 (0x09)

Frequency Control Word, High Byte.

### FREQ1 (0x0A)

Frequency Control Word, Middle Byte.

### FREQ0 (0x0B)

Frequency Control Word, Low Byte.

### MDMCFG4 (0x0C)