https://github.com/pulp-platform/axi_vga
https://github.com/pulp-platform/axi_vga
Last synced: 5 months ago
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- Host: GitHub
- URL: https://github.com/pulp-platform/axi_vga
- Owner: pulp-platform
- License: other
- Created: 2022-11-02T11:00:14.000Z (over 3 years ago)
- Default Branch: main
- Last Pushed: 2025-06-23T09:20:34.000Z (about 1 year ago)
- Last Synced: 2025-06-23T10:23:31.941Z (about 1 year ago)
- Language: SystemVerilog
- Size: 615 KB
- Stars: 5
- Watchers: 4
- Forks: 1
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- Changelog: CHANGELOG.md
- License: LICENSE
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README
# AXI VGA
This repository contains a free and open-source, fully synthesizable VGA controller requesting pixel data directly using configurable AXI bursts. It is part of the PULP ecosystem.
## Caveats
While future improvements may relax these constraints, currently:
* We only support AXI data widths of 32b to 1024b.
* The pixel size in memory must be equal to the sum of the hardware channel widths.
* The pixel size in memory must be a divisor of the data bus width.
## Reconfiguring AXI VGA
To simplify VGA reconfiguration in your project, you can include the GNU Make fragment `axi_vga.mk` in your makefile, for example:
```make
include $(shell bender path axi_vga)/axi_vga.mk
# Inject alternative register layout if needed
$(AXI_VGA_ROOT)/data/axi_vga.hjson: config/axi_vga.json
cp $< $@
# Rebuild VGA RTL
all: axi_vga
```
## Simulation
A simple standalone testbench is provided. If you have access to Questa Advanced Simulator, you can run it using the scripts provided in `vsim`:
```
make vsim
```
## Licensing
Everything in this repository is licensed under the Solderpad Hardware License 0.51 (see `LICENSE`), with the exception of the regfile RTL (`src/axi_vga_reg_*.sv`) which is generated by a fork of lowRISC's [`regtool`](https://github.com/lowRISC/opentitan/blob/master/util/regtool.py) and licensed under Apache 2.0.