https://github.com/pulp-platform/riscv-dbg

RISC-V Debug Support for our PULP RISC-V Cores
https://github.com/pulp-platform/riscv-dbg

debug riscv

Last synced: 3 months ago
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RISC-V Debug Support for our PULP RISC-V Cores

• Host: GitHub
• URL: https://github.com/pulp-platform/riscv-dbg
• Owner: pulp-platform
• License: other
• Created: 2019-01-24T11:49:31.000Z (about 6 years ago)
• Default Branch: master
• Last Pushed: 2024-07-17T16:16:40.000Z (6 months ago)
• Last Synced: 2024-08-02T17:39:59.981Z (6 months ago)
• Topics: debug, riscv
• Language: SystemVerilog
• Homepage:
• Size: 434 KB
• Stars: 205
• Watchers: 20
• Forks: 71
• Open Issues: 31
• Metadata Files:
  • Readme: README.md
  • Changelog: CHANGELOG.md
  • License: LICENSE

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README

        
# RISC-V Debug Support for various Cores

This module is an implementation of a debug unit compliant with the [RISC-V

debug specification](https://github.com/riscv/riscv-debug-spec) v0.13.1. It is

used in the [cva6](https://github.com/pulp-platform/cva6),

[cv32e40p](https://github.com/pulp-platform/cv32e40p) and

[ibex](https://github.com/lowRISC/ibex) cores.

## Implementation

We use an execution-based technique, also described in the specification, where

the core is running in a "park loop". Depending on the request made to the debug

unit via JTAG over the Debug Transport Module (DTM), the code that is being

executed is changed dynamically. This approach simplifies the implementation

side of the core, but means that the core is in fact always busy looping while

debugging.

## Features

The following features are currently supported

* Parametrizable buswidth for `XLEN=32` `XLEN=64` cores

* Accessing registers over abstract command

* Program buffer

* System bus access (only `XLEN`)

* DTM with JTAG interface

These are not implemented (yet)

* Trigger module

* Quick access using abstract commands

* Accessing memory using abstract commands

* Authentication

## Limitations

* The JTAG clock frequency needs to be lower than the system's clock frequency (see also https://github.com/pulp-platform/riscv-dbg/issues/163). 

## Tests

We use OpenOCD's [RISC-V compliance

tests](https://github.com/riscv/riscv-openocd/blob/riscv/src/target/riscv/riscv-013.c),

our custom testbench in `tb/` and

[riscv-tests/debug](https://github.com/riscv/riscv-tests/tree/master/debug).